EPM5192AJC84-20 vs EPM5192ALC84-20 比較
詳細並排比較 EPM5192AJC84-20 由 Altera 與 EPM5192ALC84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete規格比較
| 參數 | EPM5192AJC84-20 | EPM5192ALC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | UV-Erasable/OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| 最大時脈頻率 | 66.7 MHz | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS |
| 封裝 | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Operating Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount (J-Lead) | Surface Mount (PLCC socket-compatible) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in provided web data] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | Altera MAX 5000 |
| Speed Grade | — | -20 (20 ns pin-to-pin delay) |
| Terminal Pitch | — | 1.270 mm |
| Terminal Form | — | J-bend |
| Package Code | — | QCCJ (PLCC-84) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Family | — | MAX 5000 EPLD |
| I/O Compatibility | — | TTL-compatible |
| Configuration Memory | — | EPROM (UV-erasable) |