EPM5192ALC84-15 vs EPM5192ALI84-15 Comparison
Detailed side-by-side comparison of EPM5192ALC84-15 by Altera and EPM5192ALI84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192ALC84-15 | EPM5192ALI84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | MAX 5000 |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | — |
| Propagation Delay (tPD) | 15 ns | 25 ns (-15 speed grade) |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS, non-volatile EPROM/OTP |
| Programmability | UV-erasable window / OTP | One-Time Programmable (windowless) |
| Package | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin PQCC (PLCC, J-Lead) |
| Operating Temperature Grade | Commercial | Industrial |
| Terminal Form | J-BEND | J Bend (J-Lead) |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Product Type | — | UV-Erasable / OTP Complex PLD |
| Logic Macrocells | — | 192 |
| Bidirectional I/O Pins | — | 64 |
| Maximum Total Inputs | — | 72 |
| JEDEC JESD-30 Code | — | S-PQCC-J84 |
| Operating Temperature Range | — | [DATA_NEEDED: temperature range] |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| Mounting Type | — | Surface Mount (PLCC socket compatible) |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |