EPM5192ALC84-15 vs EPM5192ALI84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192ALC84-15 sa pamamagitan ng Altera at EPM5192ALI84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192ALC84-15 | EPM5192ALI84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | MAX 5000 |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | — |
| Propagation Delay (tPD) | 15 ns | 25 ns (-15 speed grade) |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS, non-volatile EPROM/OTP |
| Programmability | UV-erasable window / OTP | One-Time Programmable (windowless) |
| Packhaging | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin PQCC (PLCC, J-Lead) |
| Operating Temperature Grade | Commercial | Industrial |
| Terminal Form | J-BEND | J Bend (J-Lead) |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Product Type | — | UV-Erasable / OTP Complex PLD |
| Logic Macrocells | — | 192 |
| Bidirectional I/O Pins | — | 64 |
| Maximum Total Inputs | — | 72 |
| JEDEC JESD-30 Code | — | S-PQCC-J84 |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |
| Uri ng Pagpapasok | — | Surface Mount (PLCC socket compatible) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |