EPM5192AQM100-20 vs EPM5192AQI100-20 Comparison
Detailed side-by-side comparison of EPM5192AQM100-20 by Intel and EPM5192AQI100-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteAltera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AQM100-20 | EPM5192AQI100-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $18.90 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | β |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | β |
| Number of LABs | 12 | β |
| User I/O Lines | 64 | β |
| Dedicated Inputs | 7 | 7 |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | β |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | β |
| Package | 100-pin PQFP (JESD-30 code R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Mounting Type | Surface Mount | Surface Mount (PQFP) |
| Process Technology | CMOS EPROM-based | β |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | β |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | β |
| External Clock Input | Yes (global clock pin) | β |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | β |
| Supply Voltage | [DATA_NEEDED: VCC range from datasheet] | [DATA_NEEDED: VCC range] |
| RoHS Status | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS compliance status] |
| Family | β | MAX 5000 EPLD |
| Device Series | β | EPM5192 |
| Technology | β | CMOS, UV-erasable EPROM |
| Propagation Delay | β | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | β | 12 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Macrocell Count | β | 192 |
| I/O Pins | β | 64 bidirectional |
| JEDEC Package Outline | β | R-PQFP-G100 |
| Operating Temperature | β | Industrial grade ("I" suffix) |
| Architecture | β | Classic EPLD, deterministic timing |
| Design Tool | β | Altera MAX+PLUS II (legacy) |