EPM5192AQM100-20 vs EPM5192AQI100-20 Comparación
Comparación detallada lado a lado de EPM5192AQM100-20 por Intel y EPM5192AQI100-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteAltera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteComparación de especificaciones
| Parámetro | EPM5192AQM100-20 | EPM5192AQI100-20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $18,90 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | — |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | — |
| Number of LABs | 12 | — |
| User I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Encapsulado | 100-pin PQFP (JESD-30 code R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Tipo de montaje | Surface Mount | Surface Mount (PQFP) |
| Process Technology | CMOS EPROM-based | — |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | — |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | — |
| External Clock Input | Yes (global clock pin) | — |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | — |
| Tensión de alimentación | [DATA_NEEDED: VCC range from datasheet] | [DATA_NEEDED: VCC range] |
| Estado RoHS | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 5000 EPLD |
| Device Series | — | EPM5192 |
| Technology | — | CMOS, UV-erasable EPROM |
| Propagation Delay | — | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Macrocell Count | — | 192 |
| I/O Pins | — | 64 bidirectional |
| JEDEC Package Outline | — | R-PQFP-G100 |
| Temperatura de funcionamiento | — | Industrial grade ("I" suffix) |
| Architecture | — | Classic EPLD, deterministic timing |
| Design Tool | — | Altera MAX+PLUS II (legacy) |