EPM5192AQM100-20 vs EPM5192AQI100-20 对比

详细并排对比 EPM5192AQM100-20 出自 Intel 和 EPM5192AQI100-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。

Intel

EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera

EPM5192AQM100-20 Obsolete

Altera

EPM5192AQI100-20 Obsolete

参数	EPM5192AQM100-20	EPM5192AQI100-20
品牌	Intel	Altera
分类	FPGA & CPLD	FPGA & CPLD
生命周期状态	Obsolete	Obsolete
库存状态	有库存	有库存
单价（USD）	$8.20	$18.90
Device Family	MAX 5000 (EPLD / classic CPLD)	—
Logic Elements	192 macrocells across 12 Logic Array Blocks (LABs)	—
Number of LABs	12	—
User I/O Lines	64	—
Dedicated Inputs	7	7
Pin-to-Pin Propagation Delay (tPD)	33 ns	—
Maximum Clock Frequency (fMAX)	66.7 MHz	—
封装	100-pin PQFP (JESD-30 code R-PQFP-G100)	100-pin PQFP (R-PQFP-G100)
安装类型	Surface Mount	Surface Mount (PQFP)
Process Technology	CMOS EPROM-based	—
Configuration Memory	On-chip EPROM (non-volatile, one-time programmable in this package)	—
Boundary-Scan Test	JTAG / IEEE 1149.1 compatible	—
External Clock Input	Yes (global clock pin)	—
Operating Temperature Grade	[DATA_NEEDED: explicit temperature grade from datasheet]	—
电源电压	[DATA_NEEDED: VCC range from datasheet]	[DATA_NEEDED: VCC range]
RoHS 状态	[DATA_NEEDED: verified from manufacturer product page]	[DATA_NEEDED: RoHS compliance status]
Family	—	MAX 5000 EPLD
Device Series	—	EPM5192
Technology	—	CMOS, UV-erasable EPROM
Propagation Delay	—	20 ns (speed grade -20)
Logic Array Blocks (LABs)	—	12
Interconnect	—	Programmable Interconnect Array (PIA)
Macrocell Count	—	192
I/O Pins	—	64 bidirectional
JEDEC Package Outline	—	R-PQFP-G100
工作温度	—	Industrial grade ("I" suffix)
Architecture	—	Classic EPLD, deterministic timing
Design Tool	—	Altera MAX+PLUS II (legacy)