EPM5192C-2 vs EPM5192AQC-2 Comparison
Detailed side-by-side comparison of EPM5192C-2 by Altera and EPM5192AQC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192C-2 | EPM5192AQC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | Complex Programmable Logic Device (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (PIA, typical) | 45 ns | — |
| Maximum Operating Frequency | 50 MHz | — |
| Process Technology | CMOS | CMOS |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -2 | — |
| Programming Interface | JTAG / Altera MAX+ programming | JTAG (IEEE 1149.1) boundary scan |
| RoHS Status | unknown | [DATA_NEEDED: confirmed compliance status] |
| Lead-Free | unknown | — |
| Series | — | MAX 5000 (EPM5192) |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 45 ns (-2 speed grade) |
| Maximum Clock Frequency | — | [DATA_NEEDED: max fMAX for -2 grade] |
| Switch Matrix | — | UV-Erasable / OTP (windowless on AQC package) |
| Package | — | 100-pin PQFP (R-PQFP-G100) |
| Lead Pitch | — | 0.635 mm |
| Terminal Form | — | Gull-wing |
| Operating Temperature | — | [DATA_NEEDED: commercial / industrial / military grade] |
| Mounting Type | — | Surface Mount |