EPM5192C-2 vs EPM5192AQC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192C-2 sa pamamagitan ng Altera at EPM5192AQC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192C-2 | EPM5192AQC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | Complex Programmable Logic Device (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (PIA, typical) | 45 ns | — |
| Maximum Operating Frequency | 50 MHz | — |
| Process Technology | CMOS | CMOS |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -2 | — |
| Programming Interface | JTAG / Altera MAX+ programming | JTAG (IEEE 1149.1) boundary scan |
| Tindminan RoHS | unknown | [DATA_NEEDED: confirmed compliance status] |
| Lead-Free | unknown | — |
| Series | — | MAX 5000 (EPM5192) |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 45 ns (-2 speed grade) |
| Maksimum na Taktiko ng Oras | — | [DATA_NEEDED: max fMAX for -2 grade] |
| Switch Matrix | — | UV-Erasable / OTP (windowless on AQC package) |
| Packhaging | — | 100-pin PQFP (R-PQFP-G100) |
| Lead Pitch | — | 0.635 mm |
| Terminal Form | — | Gull-wing |
| Temperature na Operasyon | — | [DATA_NEEDED: commercial / industrial / military grade] |
| Uri ng Pagpapasok | — | Surface Mount |