EPM5192GI vs EPM5192GM Comparison
Detailed side-by-side comparison of EPM5192GI by Altera and EPM5192GM by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GI | EPM5192GM |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.95 | $58.00 |
| Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | UV Erasable Programmable Logic Device (PLD) |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS |
| Macrocells | 192 | β |
| Logic Array Blocks (LABs) | 16 (12 macrocells per LAB) | β |
| User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | β |
| Total Inputs | 72 | β |
| Propagation Delay (tPD) | 55 ns | β |
| Maximum Internal Frequency (fCNT) | 33.3 MHz | β |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | β |
| Operating Temperature | -40 C to +85 C (Industrial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Package Type | 84-pin PGA (Pin Grid Array), ceramic with quartz window | β |
| Programmable | UV-erasable (windowed) and OTP variants | β |
| Mounting Type | Through-hole (PGA) | Through-Hole (PGA) |
| RoHS Status | [DATA_NEEDED: not confirmed in verified web data] | Non-compliant (contains lead in ceramic PGA) |
| Product Family | β | MAX 5000 |
| Number of Macrocells | β | 192 |
| Usable Gates | β | 3,750 |
| Pin-to-Pin Delay (tPD) | β | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | β | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | β | 55 ns |
| Package | β | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Erasure Method | β | UV (windowed ceramic package) |
| Supply Voltage | β | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | β | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | β | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | β | JTAG-compatible (per MAX 5000 family) |