EPM5192GI vs EPM5192GM 比較

詳細な並列比較: EPM5192GI メーカー: Altera および EPM5192GM メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192GI EPM5192GM
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $18.95 $58.00
Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) UV Erasable Programmable Logic Device (PLD)
Technology CMOS EPROM (UV-erasable / OTP) CMOS
Macrocells 192 —
Logic Array Blocks (LABs) 16 (12 macrocells per LAB) —
User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 55 ns —
Maximum Internal Frequency (fCNT) 33.3 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
動作温度 -40 C to +85 C (Industrial) [DATA_NEEDED: commercial/industrial/military grade]
Package Type 84-pin PGA (Pin Grid Array), ceramic with quartz window —
Programmable UV-erasable (windowed) and OTP variants —
実装タイプ Through-hole (PGA) Through-Hole (PGA)
RoHS ステータス [DATA_NEEDED: not confirmed in verified web data] Non-compliant (contains lead in ceramic PGA)
Product Family — MAX 5000
Number of Macrocells — 192
Usable Gates — 3,750
Pin-to-Pin Delay (tPD) — 15 ns (fastest speed grade); 55 ns (this part)
Counter Frequency (fCNT) — up to 76.9 MHz
Propagation Delay (tPD, this part) — 55 ns
パッケージ — CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed)
Erasure Method — UV (windowed ceramic package)
電源電圧 — [DATA_NEEDED: typical VCC range]
Maximum User I/O — [DATA_NEEDED: exact I/O count for CPGA-84]
Process Node — [DATA_NEEDED: CMOS process geometry]
Programming Interface — JTAG-compatible (per MAX 5000 family)

データシート&リソース

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