EPM5192GM - 192-Cell MAX 5000 UV PLD, 55ns | Altera
MPN: EPM5192GM β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85 | $850.00 |
| 100 | $75 | $7,500.00 |
| 500 | $65 | $32,500.00 |
| 1,000 | $58 | $58,000.00 |
Drop-in alternatives for EPM5192GM β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192GM883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$142 / Unit
View Datasheet βEPM5192GC84-1
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM5192GC-1
β Drop-Inβ In Stock
$17.85 / Unit
View Datasheet βEPM5192GC-2
β Drop-Inβ In Stock
$92 / Unit
View Datasheet βEPM5192GI
β Drop-Inβ In Stock
$18.95 / Unit
View Datasheet βEPM5192GM Maximum Ratings & Electrical Characteristics
| Product Family | MAX 5000 |
| Device Type | UV Erasable Programmable Logic Device (PLD) |
| Technology | CMOS |
| Number of Macrocells | 192 |
| Usable Gates | 3,750 |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | 55 ns |
| Package | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Mounting Type | Through-Hole (PGA) |
| Erasure Method | UV (windowed ceramic package) |
| RoHS Status | Non-compliant (contains lead in ceramic PGA) |
| Programming Interface | JTAG-compatible (per MAX 5000 family) |
EPM5192GM Pin Configuration
| Pin 1 | I/O β User I/O pin (function programmable) |
| Pin 2 | I/O β User I/O pin (function programmable) |
| Pin 3 | I/O β User I/O pin (function programmable) |
| Pin 4 | I/O β User I/O pin (function programmable) |
| Pin 5 | I/O β User I/O pin (function programmable) |
| Pin 6 | I/O β User I/O pin (function programmable) |
| Pin 7 | I/O β User I/O pin (function programmable) |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O pin (function programmable) |
| Pin 10 | I/O β User I/O pin (function programmable) |
| Pin 11 | I/O β User I/O pin (function programmable) |
| Pin 12 | I/O β User I/O pin (function programmable) |
| Pin 13 | I/O β User I/O pin (function programmable) |
| Pin 14 | I/O β User I/O pin (function programmable) |
| Pin 15 | I/O β User I/O pin (function programmable) |
| Pin 16 | I/O β User I/O pin (function programmable) |
| Pin 17 | I/O β User I/O pin (function programmable) |
| Pin 18 | GND β Ground |
| Pin 19 | I/O β User I/O pin (function programmable) |
| Pin 20 | I/O β User I/O pin (function programmable) |
| Pin 21 | I/O β User I/O pin (function programmable) |
| Pin 22 | I/O β User I/O pin (function programmable) |
| Pin 23 | I/O β User I/O pin (function programmable) |
| Pin 24 | I/O β User I/O pin (function programmable) |
| Pin 25 | I/O β User I/O pin (function programmable) |
| Pin 26 | I/O β User I/O pin (function programmable) |
| Pin 27 | I/O β User I/O pin (function programmable) |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O pin (function programmable) |
| Pin 30 | I/O β User I/O pin (function programmable) |
| Pin 31 | I/O β User I/O pin (function programmable) |
| Pin 32 | I/O β User I/O pin (function programmable) |
| Pin 33 | I/O β User I/O pin (function programmable) |
| Pin 34 | I/O β User I/O pin (function programmable) |
| Pin 35 | I/O β User I/O pin (function programmable) |
| Pin 36 | I/O β User I/O pin (function programmable) |
| Pin 37 | I/O β User I/O pin (function programmable) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin (function programmable) |
| Pin 40 | I/O β User I/O pin (function programmable) |
| Pin 41 | I/O β User I/O pin (function programmable) |
| Pin 42 | I/O β User I/O pin (function programmable) |
| Pin 43 | I/O β User I/O pin (function programmable) |
| Pin 44 | I/O β User I/O pin (function programmable) |
| Pin 45 | I/O β User I/O pin (function programmable) |
| Pin 46 | I/O β User I/O pin (function programmable) |
| Pin 47 | I/O β User I/O pin (function programmable) |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β User I/O pin (function programmable) |
| Pin 50 | I/O β User I/O pin (function programmable) |
| Pin 51 | I/O β User I/O pin (function programmable) |
| Pin 52 | I/O β User I/O pin (function programmable) |
| Pin 53 | I/O β User I/O pin (function programmable) |
| Pin 54 | I/O β User I/O pin (function programmable) |
| Pin 55 | I/O β User I/O pin (function programmable) |
| Pin 56 | I/O β User I/O pin (function programmable) |
| Pin 57 | I/O β User I/O pin (function programmable) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O pin (function programmable) |
| Pin 60 | I/O β User I/O pin (function programmable) |
| Pin 61 | I/O β User I/O pin (function programmable) |
| Pin 62 | I/O β User I/O pin (function programmable) |
| Pin 63 | I/O β User I/O pin (function programmable) |
| Pin 64 | I/O β User I/O pin (function programmable) |
| Pin 65 | I/O β User I/O pin (function programmable) |
| Pin 66 | I/O β User I/O pin (function programmable) |
| Pin 67 | I/O β User I/O pin (function programmable) |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O pin (function programmable) |
| Pin 70 | I/O β User I/O pin (function programmable) |
| Pin 71 | I/O β User I/O pin (function programmable) |
| Pin 72 | I/O β User I/O pin (function programmable) |
| Pin 73 | I/O β User I/O pin (function programmable) |
| Pin 74 | I/O β User I/O pin (function programmable) |
| Pin 75 | I/O β User I/O pin (function programmable) |
| Pin 76 | I/O β User I/O pin (function programmable) |
| Pin 77 | I/O β User I/O pin (function programmable) |
| Pin 78 | GND β Ground |
| Pin 79 | I/O β User I/O pin (function programmable) |
| Pin 80 | I/O β User I/O pin (function programmable) |
| Pin 81 | I/O β User I/O pin (function programmable) |
| Pin 82 | I/O β User I/O pin (function programmable) |
| Pin 83 | I/O β User I/O pin (function programmable) |
| Pin 84 | I/O β User I/O pin (function programmable) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192GM is suitable for 6 applications: Legacy Industrial Control Logic, Microprocessor Glue Logic, Military / Aerospace Systems, Prototype Development and Engineering Labs, Bus Address Decoding and Chip Select Generation, State Machine and Sequencing Controllers.
Legacy Industrial Control Logic
The EPM5192GM's 192 macrocells and 3,750 usable gates provide ample capacity for state machines and discrete logic replacement in legacy industrial control systems. With a deterministic 55 ns pin-to-pin delay, the device excels at bus decoding, sequencing, and I/O expansion in PLC backplanes. The MAX 5000 architecture gives predictable timing that many long-lifecycle industrial programs depend on. Designers use the EPM5192GM to consolidate dozens of 74-series TTL/CMOS chips into a single windowed PLD for maintainability, while preserving 5 V I/O compatibility with existing backplane logic.
Recommended
Microprocessor Glue Logic
The EPM5192GM was designed for the era of DEC, Intel, and Motorola microprocessor systems, where 'glue logic' β address decoding, wait-state generation, bus arbitration, and interrupt steering β had to be implemented in discrete TTL. The device's 192 macrocells and high pin count comfortably handle full 24- or 32-bit address decoding plus peripheral chip-select generation. Pin-to-pin delays of 55 ns suit 8- and 16-bit bus architectures; faster speed grades (down to 15 ns) handle 32-bit systems. The deterministic timing simplifies worst-case timing analysis for mission-critical embedded systems.
Recommended
Military / Aerospace Systems
The EPM5192GM's ceramic windowed PGA package and MIL-STD-883 processing options make it a candidate for military and aerospace applications where hermetic packaging and radiation tolerance are valued. The MAX 5000 family is supported by Altera with 883B variants qualified for MIL-STD-883 Class B screening. The 192-macrocell density is sufficient for avionics interface logic, radar timing, and guidance subsystems that demand deterministic SPLD behavior. Designers favour the device when QML-qualified, hermetic-PGA parts are required by program specifications.
Recommended
Prototype Development and Engineering Labs
The UV-erasable windowed ceramic package of the EPM5192GM makes it an ideal device for engineering laboratories where iterative design changes are routine. Engineers can erase the part under a UV lamp in 20-30 minutes and re-program it many times during development. The 192-macrocell capacity accommodates full prototype subsystems, and the MAX 5000 family supports JTAG-compatible programming via Altera's legacy programming tools. Once the design stabilises, the engineer migrates to the OTP ceramic PGA (EPM5192GC) or EEPROM variant (EPM5192GI) for production.
Recommended
Bus Address Decoding and Chip Select Generation
The EPM5192GM's 192 macrocells and high I/O count make it ideally suited to bus address decoding and chip-select generation in 16- and 32-bit microprocessor systems. Its deterministic 55 ns tPD provides worst-case timing margins that are easy to verify in datasheet-based static timing analysis. The MAX 5000 architecture supports both active-high and active-low output polarities, with internal feedback that allows registered outputs without external glue logic. Designers use the device to replace PAL/GAL-based decode trees that would otherwise consume board area and power.
Recommended
State Machine and Sequencing Controllers
The EPM5192GM is a strong choice for implementing Moore and Mealy state machines in deterministic, hardware-described form. Its 192 macrocells accommodate state machines with 16-32 states plus extensive output decoding, while the high I/O count supports wide control buses. Pin-to-pin delays in the 15-55 ns range are well-matched to industrial sequencing timelines. The MAX 5000 family provides configurable output macrocells that can be registered or combinatorial, with feedback paths suitable for sequential logic. Designers favour the device for fail-safe machine control where predictable timing is essential.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192GM β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192GM883B | EPM5192GC84-1 | EPM5192GC-1 | EPM5192GC-2 | EPM5192GI |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-84 (windowed) | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same |
| Erasure Method | UV (windowed ceramic) | UV (windowed) | OTP (no window) | OTP (no window) | OTP (no window) | EEPROM |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| tPD (ns) | 55 | 55 | 55 | 55 (-1 grade) | 70-75 (-2 grade, slower) | 55 |
| Military Grade (MIL-STD-883) | No (commercial) | Yes (Class B) | No | No | No | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Reprogrammability | Yes (UV erase + reprogram) | Yes (UV erase + reprogram) | No (OTP) | No (OTP) | No (OTP) | Yes (in-system EEPROM) |
Key Differentiators
- UV-erasable windowed ceramic package (vs EPM5192GC-1)
- Standard commercial (non-883) screening (vs EPM5192GM883B)
- UV (optical) erasure mechanism (vs EPM5192GI)
Design Notes
The EPM5192GM operates from a single 5 V supply. Place a 0.1 Β΅F ceramic decoupling capacitor near every VCC pin (multiple pins on PGA-84) and a 10 Β΅F bulk capacitor at the board's power entry. Use a low-impedance ground plane; the ceramic PGA package relies on multiple GND pins for return paths. Decoupling inductance must be minimised β the device's 55 ns tPD means internal switching edges can reach MHz-range harmonics.
Use a socket for the EPM5192GM in prototype designs. The CPGA-84 ceramic package is fragile and expensive; a PGA-84 machine-pin socket allows easy removal for UV erasure and re-programming. Ensure the socket has adequate mechanical retention β the ceramic package is heavier than plastic and can vibrate loose in high-shock environments. For production designs, migrate to the EPM5192GC (OTP) or EPM5192GI (EEPROM) variant in the same CPGA-84 footprint.
Do not power the EPM5192GM outside its 5 V Β±5% supply range β the device is not 3.3 V tolerant and over-voltage can permanently damage the EEPROM/UV cells. Do not use the part in designs that require 3.3 V I/O interfacing; use a modern MAX II/MAX V CPLD instead. Avoid exposure to UV light sources other than the dedicated eraser β sunlight and fluorescent lamps can erase the device over time.
The ceramic PGA-84 package provides good thermal performance. At room temperature, the EPM5192GM dissipates modest power (~0.5-1 W typical) and does not require a heatsink. In enclosed or high-temperature industrial environments, verify junction temperature by measuring case temperature; the ceramic package simplifies this with a thermocouple.
Compliance Information
Ceramic PGA package contains lead-bearing solder/termination finish and is RoHS-non-compliant per exemption for military/aerospace. MIL-STD-883 variant (EPM5192GM883B) is qualified for Class B screening.
