EPM5192GM vs EPM5192GC-2 Comparison

Detailed side-by-side comparison of EPM5192GM by Altera and EPM5192GC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192GM EPM5192GC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (PLD) —
Technology CMOS CMOS EPROM
Number of Macrocells 192 —
Usable Gates 3,750 —
Pin-to-Pin Delay (tPD) 15 ns (fastest speed grade); 55 ns (this part) —
Counter Frequency (fCNT) up to 76.9 MHz —
Propagation Delay (tPD, this part) 55 ns —
Package CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) —
Mounting Type Through-Hole (PGA) Through-hole (PGA socket)
Erasure Method UV (windowed ceramic package) —
Supply Voltage [DATA_NEEDED: typical VCC range] —
Maximum User I/O [DATA_NEEDED: exact I/O count for CPGA-84] —
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] Commercial (0C to +70C)
RoHS Status Non-compliant (contains lead in ceramic PGA) Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing)
Process Node [DATA_NEEDED: CMOS process geometry] —
Programming Interface JTAG-compatible (per MAX 5000 family) —
Family — MAX 5000
Macrocells — 192
Logic Array Blocks — 16 (LABs of 16 macrocells each)
Usable I/O Pins — [DATA_NEEDED: exact user I/O count for PGA package]
Propagation Delay (tPD) — 12 ns typical (-2 grade)
Counter Frequency — 100 MHz minimum
Supply Voltage (VCC) — 5 V nominal
Programmable Technology — UV-erasable / one-time programmable
Programming Toolchain — Altera MAX+PLUS II
Package Type — Pin Grid Array (PGA), ceramic
Speed Grade — -2

Datasheets & Resources

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