EPM5192GM vs EPM5192GC-2 比較
詳細並排比較 EPM5192GM 由 Altera 與 EPM5192GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GM | EPM5192GC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (PLD) | — |
| Technology | CMOS | CMOS EPROM |
| Number of Macrocells | 192 | — |
| Usable Gates | 3,750 | — |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) | — |
| Counter Frequency (fCNT) | up to 76.9 MHz | — |
| Propagation Delay (tPD, this part) | 55 ns | — |
| 封裝 | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) | — |
| 安裝類型 | Through-Hole (PGA) | Through-hole (PGA socket) |
| Erasure Method | UV (windowed ceramic package) | — |
| 供應電壓 | [DATA_NEEDED: typical VCC range] | — |
| Maximum User I/O | [DATA_NEEDED: exact I/O count for CPGA-84] | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | Commercial (0C to +70C) |
| RoHS 狀態 | Non-compliant (contains lead in ceramic PGA) | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Process Node | [DATA_NEEDED: CMOS process geometry] | — |
| Programming Interface | JTAG-compatible (per MAX 5000 family) | — |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Speed Grade | — | -2 |