EPM5192JC-1 vs EPM5192C-2 Comparison
Detailed side-by-side comparison of EPM5192JC-1 by Altera and EPM5192C-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-1 | EPM5192C-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.40 | $13.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | Complex Programmable Logic Device (CPLD) |
| Technology | CMOS, UV-Erasable / OTP | β |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | β |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | β |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| User I/O Pins | 84 | 64 |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | β |
| JEDEC Package Code | S-CQCC-J84 | β |
| Operating Temperature | 0 C to +70 C (commercial) | β |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | EEPROM (non-volatile) |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | JTAG / Altera MAX+ programming |
| Process | CMOS EPROM | β |
| I/O Standard | TTL/CMOS 5 V compatible | β |
| Logic Array Blocks (LABs) | β | 12 |
| Dedicated Inputs | β | 7 |
| External Clock Inputs | β | 1 |
| Propagation Delay (PIA, typical) | β | 45 ns |
| Maximum Operating Frequency | β | 50 MHz |
| Process Technology | β | CMOS |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA) |
| Speed Grade | β | -2 |
| RoHS Status | β | unknown |
| Lead-Free | β | unknown |