EPM5192JC-1 vs EPM5192C-2 比較
詳細並排比較 EPM5192JC-1 由 Altera 與 EPM5192C-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-1 | EPM5192C-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | Complex Programmable Logic Device (CPLD) |
| Technology | CMOS, UV-Erasable / OTP | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| User I/O Pins | 84 | 64 |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| 工作溫度 | 0 C to +70 C (commercial) | — |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | EEPROM (non-volatile) |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | JTAG / Altera MAX+ programming |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (PIA, typical) | — | 45 ns |
| Maximum Operating Frequency | — | 50 MHz |
| Process Technology | — | CMOS |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -2 |
| RoHS 狀態 | — | unknown |
| Lead-Free | — | unknown |