EPM5192JC-1 vs EPM5192IC-1 Comparison
Detailed side-by-side comparison of EPM5192JC-1 by Altera and EPM5192IC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-1 | EPM5192IC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.40 | $13.95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Technology | CMOS, UV-Erasable / OTP | CMOS, UV-erasable, in-system programmable |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 3750 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | β |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (nominal 5 V) |
| User I/O Pins | 84 | β |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | β |
| JEDEC Package Code | S-CQCC-J84 | β |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | β |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | JTAG / IEEE Std 1149.1 boundary scan |
| Process | CMOS EPROM | β |
| I/O Standard | TTL/CMOS 5 V compatible | β |
| Dedicated Inputs | β | 7 |
| I/O Pins | β | 64 |
| Pin-to-Pin Delay (tPD) | β | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | β | 76.9 MHz |
| Package | β | 68-pin ceramic J-lead (IC-1 suffix) |
| Security Bit | β | Yes (design protection) |
| Supply Current (Icc, typical) | β | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | β | [DATA_NEEDED: IOH/IOL] mA |