EPM5192JC-1 vs EPM5192IC-1 비교
다음의 상세 나란히 비교: EPM5192JC-1 제조: Altera 및 EPM5192IC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JC-1 | EPM5192IC-1 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $22.40 | $13.95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Technology | CMOS, UV-Erasable / OTP | CMOS, UV-erasable, in-system programmable |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 3750 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (nominal 5 V) |
| User I/O Pins | 84 | — |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| 동작 온도 | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | JTAG / IEEE Std 1149.1 boundary scan |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| 패키지 | — | 68-pin ceramic J-lead (IC-1 suffix) |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |