EPM5192JC-1 vs EPM5192IC-1 Vergleich
Detaillierter Direktvergleich von EPM5192JC-1 von Altera und EPM5192IC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC-1 | EPM5192IC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,40 | $13,95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Technology | CMOS, UV-Erasable / OTP | CMOS, UV-erasable, in-system programmable |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 3750 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (nominal 5 V) |
| User I/O Pins | 84 | — |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | JTAG / IEEE Std 1149.1 boundary scan |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Gehäuse | — | 68-pin ceramic J-lead (IC-1 suffix) |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |