EPM5192JC-1N vs EPM5192LC-2N Comparison
Detailed side-by-side comparison of EPM5192JC-1N by Altera and EPM5192LC-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-1N | EPM5192LC-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 3750 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Package | 84-pin Ceramic Quad Flat Pack (CQFP) | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| Operating Temperature | [DATA_NEEDED: industrial/commercial temperature range] | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programming Interface | JTAG / Altera ByteBlaster | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Speed Grade | — | -2 (tPD approximately 25 ns) |
| Propagation Delay (typical) | — | 25 ns |
| Supply Voltage | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| Mounting Type | — | Surface Mount (LC package) |
| RoHS Status | — | Compliant (per -N lead-free suffix) |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |