EPM5192JI-1 vs EPM5192JC Comparison
Detailed side-by-side comparison of EPM5192JI-1 by Intel and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JI-1 | EPM5192JC |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Process Technology | CMOS EPROM | CMOS EPROM (UV-erasable) |
| Package | 84-pin JLCC (Windowed ceramic J-lead) | 68-pin PLCC (JC) windowed ceramic |
| Operating Temperature | Industrial, -40 C to +85 C | [DATA_NEEDED: commercial / industrial / military grade] |
| Configuration Memory | UV-erasable EPROM | — |
| Programming Method | External EPROM programmer (via programming hardware) | UV-erase + EPROM programmer |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera marking not RoHS] |
| Speed Grade | -1 (slowest grade in EPM5192 family) | — |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Mounting Type | — | Surface Mount |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Supply Voltage | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |