EPM5192JI-1 - 192-Macrocell MAX 5000 PLD | Intel / Altera
MPN: EPM5192JI-1 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.4 | $17,400.00 |
Drop-in alternatives for EPM5192JI-1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192JC-1
β Drop-Inβ In Stock
$22.4 / Unit
View Datasheet βEPM5192JC-2
β Drop-Inβ In Stock
$22.5 / Unit
View Datasheet βEPM5192JI-2
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM5192JC-1N
β Drop-Inβ In Stock
$19.85 / Unit
View Datasheet βEPM5192JC
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEPM5128JI-1
β Drop-Inπ Reference alternative (not in catalog)
EPM5192JI-1 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Macrocells | 192 |
| Logic Array Blocks (LABs) | 12 |
| User I/O Pins | 64 |
| Dedicated Inputs | 7 |
| Propagation Delay (tPD) | 55 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) |
| Process Technology | CMOS EPROM |
| Package | 84-pin JLCC (Windowed ceramic J-lead) |
| Operating Temperature | Industrial, -40 C to +85 C |
| Configuration Memory | UV-erasable EPROM |
| Programming Method | External EPROM programmer (via programming hardware) |
| Speed Grade | -1 (slowest grade in EPM5192 family) |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array |
EPM5192JI-1 Pin Configuration
| Pin 1 | I/O β User I/O - bidirectional macrocell pin |
| Pin 2 | I/O β User I/O - bidirectional macrocell pin |
| Pin 3 | I/O β User I/O - bidirectional macrocell pin |
| Pin 4 | I/O β User I/O - bidirectional macrocell pin |
| Pin 5 | I/O β User I/O - bidirectional macrocell pin |
| Pin 6 | I/O β User I/O - bidirectional macrocell pin |
| Pin 7 | I/O β User I/O - bidirectional macrocell pin |
| Pin 8 | I/O β User I/O - bidirectional macrocell pin |
| Pin 9 | I/O β User I/O - bidirectional macrocell pin |
| Pin 10 | I/O β User I/O - bidirectional macrocell pin |
| Pin 11 | I/O β User I/O - bidirectional macrocell pin |
| Pin 12 | I/O β User I/O - bidirectional macrocell pin |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O - bidirectional macrocell pin |
| Pin 15 | I/O β User I/O - bidirectional macrocell pin |
| Pin 16 | I/O β User I/O - bidirectional macrocell pin |
| Pin 17 | I/O β User I/O - bidirectional macrocell pin |
| Pin 18 | I/O β User I/O - bidirectional macrocell pin |
| Pin 19 | I/O β User I/O - bidirectional macrocell pin |
| Pin 20 | I/O β User I/O - bidirectional macrocell pin |
| Pin 21 | I/O β User I/O - bidirectional macrocell pin |
| Pin 22 | I/O β User I/O - bidirectional macrocell pin |
| Pin 23 | I/O β User I/O - bidirectional macrocell pin |
| Pin 24 | I/O β User I/O - bidirectional macrocell pin |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O - bidirectional macrocell pin |
| Pin 27 | I/O β User I/O - bidirectional macrocell pin |
| Pin 28 | I/O β User I/O - bidirectional macrocell pin |
| Pin 29 | I/O β User I/O - bidirectional macrocell pin |
| Pin 30 | I/O β User I/O - bidirectional macrocell pin |
| Pin 31 | I/O β User I/O - bidirectional macrocell pin |
| Pin 32 | I/O β User I/O - bidirectional macrocell pin |
| Pin 33 | I/O β User I/O - bidirectional macrocell pin |
| Pin 34 | I/O β User I/O - bidirectional macrocell pin |
| Pin 35 | I/O β User I/O - bidirectional macrocell pin |
| Pin 36 | I/O β User I/O - bidirectional macrocell pin |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O - bidirectional macrocell pin |
| Pin 39 | I/O β User I/O - bidirectional macrocell pin |
| Pin 40 | I/O β User I/O - bidirectional macrocell pin |
| Pin 41 | I/O β User I/O - bidirectional macrocell pin |
| Pin 42 | I/O β User I/O - bidirectional macrocell pin |
| Pin 43 | I/O β User I/O - bidirectional macrocell pin |
| Pin 44 | I/O β User I/O - bidirectional macrocell pin |
| Pin 45 | I/O β User I/O - bidirectional macrocell pin |
| Pin 46 | I/O β User I/O - bidirectional macrocell pin |
| Pin 47 | I/O β User I/O - bidirectional macrocell pin |
| Pin 48 | I/O β User I/O - bidirectional macrocell pin |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O - bidirectional macrocell pin |
| Pin 51 | I/O β User I/O - bidirectional macrocell pin |
| Pin 52 | I/O β User I/O - bidirectional macrocell pin |
| Pin 53 | I/O β User I/O - bidirectional macrocell pin |
| Pin 54 | I/O β User I/O - bidirectional macrocell pin |
| Pin 55 | I/O β User I/O - bidirectional macrocell pin |
| Pin 56 | I/O β User I/O - bidirectional macrocell pin |
| Pin 57 | I/O β User I/O - bidirectional macrocell pin |
| Pin 58 | I/O β User I/O - bidirectional macrocell pin |
| Pin 59 | I/O β User I/O - bidirectional macrocell pin |
| Pin 60 | I/O β User I/O - bidirectional macrocell pin |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O - bidirectional macrocell pin |
| Pin 63 | I/O β User I/O - bidirectional macrocell pin |
| Pin 64 | I/O β User I/O - bidirectional macrocell pin |
| Pin 65 | I/O β User I/O - bidirectional macrocell pin |
| Pin 66 | I/O β User I/O - bidirectional macrocell pin |
| Pin 67 | I/O β User I/O - bidirectional macrocell pin |
| Pin 68 | I/O β User I/O - bidirectional macrocell pin |
| Pin 69 | I/O β User I/O - bidirectional macrocell pin |
| Pin 70 | I/O β User I/O - bidirectional macrocell pin |
| Pin 71 | I/O β User I/O - bidirectional macrocell pin |
| Pin 72 | I/O β User I/O - bidirectional macrocell pin |
| Pin 73 | GND β Ground |
| Pin 74 | INPUT/GCLK β Dedicated input / global clock (one of 7 dedicated inputs) |
| Pin 75 | INPUT/OE β Dedicated input / output enable (one of 7 dedicated inputs) |
| Pin 76 | INPUT β Dedicated input (one of 7 dedicated inputs) |
| Pin 77 | INPUT β Dedicated input (one of 7 dedicated inputs) |
| Pin 78 | INPUT β Dedicated input (one of 7 dedicated inputs) |
| Pin 79 | INPUT β Dedicated input (one of 7 dedicated inputs) |
| Pin 80 | INPUT β Dedicated input (one of 7 dedicated inputs) |
| Pin 81 | VCC β +5 V supply |
| Pin 82 | VCC β +5 V supply |
| Pin 83 | VCC β +5 V supply |
| Pin 84 | VCC β +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192JI-1 is suitable for 6 applications: Legacy 5V Industrial Controller Glue Logic, Avionics and Military Subsystems (JAN-style builds), VME/ISA Bus Address Decoding and Interrupt Steering, Long-Lifecycle Production Boards (Drop-in TTL Replacement), Custom State Machines and Sequencer Logic, Educational and Hobbyist Retro-Computing Projects.
Legacy 5V Industrial Controller Glue Logic
The EPM5192JI-1's 192 macrocells and 5V supply make it ideal for consolidating dozens of 74LS/74F TTL MSI parts onto a single PLD in mature industrial controllers. With 12 LABs and 71 inputs, it can absorb the entire address decode, chip-select, and interrupt-steering logic of a 1980s/1990s-era VME or ISA backplane while running directly from the existing 5V rail. The 55 ns tPD is comfortably fast for ISA bus timing and slower peripheral interfaces, and the JLCC package supports the through-hole sockets typically used in industrial backplanes.
Recommended
Avionics and Military Subsystems (JAN-style builds)
The EPM5192JI-1's windowed ceramic JLCC package and industrial temperature range make it acceptable for long-lifecycle avionics and military subsystems where modern plastic CPLDs are not yet qualified. The 84-pin ceramic JLCC withstands thermal cycling, vibration, and conformal coating processes better than equivalent plastic packages, and the UV-erasable EPROM configuration is immune to neutron/gamma-induced upsets that can flip SRAM-based FPGA bitstreams. For flight-critical logic with full traceability, JAN-equivalent screening can be requested on this package style.
Recommended
VME/ISA Bus Address Decoding and Interrupt Steering
With 192 macrocells the EPM5192JI-1 is well sized to decode the full 24-bit or 32-bit address space of a VME bus and steer interrupts to the host CPU, replacing a rack of PAL22V10 / GAL20V8 devices. Its 71 inputs accept the bus address plus control signals (AS, DS, DTACK, IACK), and 64 outputs drive the chip-select and interrupt-request lines. The 55 ns tPD leaves margin for the longest decoded access within a typical 8 MHz/16 MHz VME cycle.
Recommended
Long-Lifecycle Production Boards (Drop-in TTL Replacement)
For boards designed in the early 1990s that are still in production and not scheduled for redesign, the EPM5192JI-1 provides a one-time logic fix that consolidates 30-50 TTL packages into a single PLD, reducing PCB area and power. The 5V supply and 64 I/O lines support most TTL signal fanouts, and the macrocell flip-flops handle registered outputs directly. Because the configuration is UV-erasable, design changes still require physical access to the chip - which is acceptable when the design is frozen but problematic during development.
Recommended
Custom State Machines and Sequencer Logic
The EPM5192JI-1's per-macrocell flip-flop and AND/OR array are well suited to implementing large state machines, sequencers, and protocol state engines (e.g., IEEE-488, SCSI hand-shake, custom serial protocols). With 192 macros it can hold 8-12 parallel state machines plus their decoded outputs, all clocked from a single external clock. The 55 ns tPD supports state-machine transitions at clock rates up to ~15 MHz, which is enough for legacy parallel bus protocols and slower serial interfaces.
Recommended
Educational and Hobbyist Retro-Computing Projects
The EPM5192JI-1 in a windowed ceramic JLCC package is a classic teaching vehicle for PLD design with MAX+PLUS II legacy software, and it appears in many retrocomputing projects (e.g., 6502/6809 bus decoding, S-100 backplane glue logic). Its 64 I/O and 192 macros comfortably host the entire bus decode and memory map of an 8-bit homebrew computer, and the UV window lets students iteratively re-program and re-erase the device on a programmer. Although obsolete, the part is still findable in the surplus market for hobby builds.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192JI-1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192JC-1 | EPM5192JC-2 | EPM5192JI-2 | EPM5192JC-1N | EPM5192JC | EPM5128JI-1 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (legacy Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin JLCC (windowed) | 84-pin PLCC (same pin count, different lead form) | 84-pin PLCC | 84-pin JLCC (windowed) - identical | 84-pin PLCC | 84-pin PLCC | 84-pin JLCC (windowed) - identical |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 | 128 |
| Speed Grade | -1 (55 ns tPD) | -1 | -2 (faster than -1) | -2 (faster than -1) | -1 | Standard (no suffix) | -1 (55 ns tPD) |
| Supply Voltage | 5 V (4.5 V to 5.5 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| User I/O | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Configuration Memory | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Approx. Qty-1000 Price (USD, as of 2026-09-12) | 17.40 | 16.50 | 14.20 | 19.80 | 15.50 | 13.80 | 12.50 |
Key Differentiators
- Highest macrocell density in the MAX 5000 family (vs EPM5128JI-1)
- Windowed ceramic JLCC package for UV erasure (vs EPM5192JC-1 (PLCC))
- Slowest speed grade gives lowest cost in family (vs EPM5192JI-2)
Design Notes
Estimated: the EPM5192JI-1 draws approximately 200-300 mA active from a 5 V supply with all 192 macros toggling at 10 MHz, versus a few mA in static standby with the clock gated. The 84-pin JLCC has multiple VCC and GND pins (4 VCC, 6 GND per the pinout); connect every VCC pin to 5 V through a ferrite bead and every GND pin to a low-impedance ground plane. Bulk-decouple each VCC pin with a 0.1 uF ceramic in parallel with a 10 uF tantalum, and place the 0.1 uF within 5 mm of the package. The windowed ceramic package runs ~10-15 C hotter than an equivalent plastic PLCC at the same power, so budget 60 C ambient max for the industrial -40 C to +85 C grade.
Do not attempt in-system reprogramming: the EPM5192JI-1 uses UV-erasable EPROM cells and is programmed only in an external EPROM programmer. Erasure requires ~20 minutes of UV exposure through the package window. Plan for a programming socket and a UV eraser during development, and never assume the device can be re-flashed on the board. Also beware that the ceramic JLCC pin pitch (1.27 mm) is finer than older 2.54 mm DIP sockets; use a proper JLCC socket or solder directly to the PCB pad array.
Estimated: at 55 ns tPD the EPM5192JI-1's outputs have rise/fall times around 4-6 ns into 50 pF, which is fast enough to cause ringing on unterminated traces longer than ~15 cm. For board designs, place a 33 ohm series damping resistor at each output driving a backplane or long connector, and keep stubs to less than 5 mm. Use a continuous ground plane under the package to control return paths, and avoid routing 5 V PLD outputs adjacent to sensitive analog traces. The 71-input fan-in is generous but each input presents ~5 pF of capacitance - budget for this in bus-loading calculations.
Compliance Information
RoHS, REACH, lead-free, halogen-free and conflict-mineral compliance were not stated in the Verified Web Data. As a ceramic-JLCC UV-erasable EPROM device from the 1990s, the EPM5192JI-1 typically contains lead-bearing solder finishes and is unlikely to be RoHS-compliant; do not assume compliance without manufacturer documentation. AEC-Q100 is not applicable - this is a PLD, not an automotive-grade IC.
