EPM5192LC-1 vs EPM5192LC Comparison
Detailed side-by-side comparison of EPM5192LC-1 by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-1 | EPM5192LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $28.40 |
| Family | MAX 5000 | MAX 7000S |
| Device Type | EPLD / CPLD | β |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | β |
| Dedicated Inputs | 7 | 7 |
| User I/O | 64 | β |
| Number of Pins | 84 | β |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | β |
| Propagation Delay | 25 ns | β |
| Maximum Clock Frequency | 50 MHz | β |
| Supply Voltage | 5 V nominal (4.75 V to 5.25 V) | β |
| Technology | CMOS, UV-erasable / OTP EPROM cell | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Programmable Memory | EPROM (one-time or UV-erasable) | β |
| Speed Grade | -1 | β |
| RoHS Status | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | β | 12 |
| User I/O Pins | β | 64 |
| Global Clock Inputs | β | 1 |
| Propagation Delay (tPD) | β | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | β | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | β | JTAG IEEE 1149.1 |
| Programming Interface | β | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | β | 0C to +70C |
| Package | β | JLCC-68 (windowed ceramic, LC suffix) |
| Mounting Type | β | Surface Mount |