EPM5192LC-1 vs EPM5192LC 比較
詳細並排比較 EPM5192LC-1 由 Altera 與 EPM5192LC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-1 | EPM5192LC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 7000S |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | 7 |
| User I/O | 64 | — |
| 腳位數 | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | — |
| 最大時脈頻率 | 50 MHz | — |
| 供應電壓 | 5 V nominal (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| 工作溫度 | 0C to +70C (commercial) | — |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| RoHS 狀態 | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Global Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | — | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |
| 封裝 | — | JLCC-68 (windowed ceramic, LC suffix) |
| 安裝類型 | — | Surface Mount |