EPM5192LC-2 vs EPM5192GC-2 Comparison
Detailed side-by-side comparison of EPM5192LC-2 by Altera and EPM5192GC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-2 | EPM5192GC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | 12 ns typical (-2 grade) |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | — |
| Package | PQCC-84 (PLCC-84, J-lead, surface mount) | — |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | Commercial (0C to +70C) |
| Supply Voltage | 5 V (typical MAX 5000 family) | — |
| RoHS Status | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Speed Grade | — | -2 |
| Mounting Type | — | Through-hole (PGA socket) |