EPM5192LC-25 vs EPM5192LC-35 Comparison
Detailed side-by-side comparison of EPM5192LC-25 by Altera and EPM5192LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-25 | EPM5192LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 CPLD |
| Macrocells | 192 | — |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | — |
| Pin-to-Pin Delay (tPD) | 25 ns | 35 ns |
| Speed Grade | -25 (25 ns) | -35 |
| Package | JLCC-84 (ceramic J-lead chip carrier) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | — |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0C to +70C) per LC suffix |
| Supply Voltage | 5 V (typical, MAX 5000) | — |
| I/O Standard | TTL-compatible | TTL |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS Status | Unknown (legacy ceramic package typically non-RoHS) | Non-compliant (ceramic hermetic package) |
| Series | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| Programmable Type | — | UV-Erasable / OTP (EPROM-based) |
| Package Type | — | JLCC (J-Lead Ceramic Chip Carrier) |
| Logic Voltage | — | 5 V TTL-compatible I/O |
| Programming Method | — | Altera legacy programmer (EPROM-based) |
| Architecture | — | LAB-based with Programmable Interconnect Array (PIA) |
| Lifecycle Status | — | Obsolete - last-time-buy stock only |
| Datasheet Document | — | Altera MAX 5000 family datasheet (per alldatasheet.com) |