EPM5192LC-25 vs EPM5192LC-35 比較
詳細並排比較 EPM5192LC-25 由 Altera 與 EPM5192LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-25 | EPM5192LC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 CPLD |
| Macrocells | 192 | — |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | — |
| Pin-to-Pin Delay (tPD) | 25 ns | 35 ns |
| Speed Grade | -25 (25 ns) | -35 |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | — |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) per LC suffix |
| 供應電壓 | 5 V (typical, MAX 5000) | — |
| I/O Standard | TTL-compatible | TTL |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) | Non-compliant (ceramic hermetic package) |
| Series | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| Programmable Type | — | UV-Erasable / OTP (EPROM-based) |
| Package Type | — | JLCC (J-Lead Ceramic Chip Carrier) |
| Logic Voltage | — | 5 V TTL-compatible I/O |
| Programming Method | — | Altera legacy programmer (EPROM-based) |
| Architecture | — | LAB-based with Programmable Interconnect Array (PIA) |
| 生命週期狀態 | — | Obsolete - last-time-buy stock only |
| Datasheet Document | — | Altera MAX 5000 family datasheet (per alldatasheet.com) |