EPM5192LC vs EPM5192LC-1 Comparison
Detailed side-by-side comparison of EPM5192LC by Altera and EPM5192LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Global Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | — |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Operating Temperature (commercial) | 0C to +70C | — |
| Package | JLCC-68 (windowed ceramic, LC suffix) | — |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Device Type | — | EPLD / CPLD |
| Logic Gates | — | 3750 (typical usable) |
| User I/O | — | 64 |
| Number of Pins | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| Maximum Clock Frequency | — | 50 MHz |
| Supply Voltage | — | 5 V nominal (4.75 V to 5.25 V) |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Operating Temperature | — | 0C to +70C (commercial) |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |
| Speed Grade | — | -1 |