EPM7096LC68-7 vs EPM7096QC100-10 Comparison
Detailed side-by-side comparison of EPM7096LC68-7 by Intel and EPM7096QC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 ObsoleteSpecification Comparison
| Parameter | EPM7096LC68-7 | EPM7096QC100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.10 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (EEPROM-based) | β |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | β |
| User I/O Pins | 52 | 76 |
| Package | 68-pin J-Lead PLCC (LC68) | 100-pin PQFP (R-PQFP-G100, 20Γ14 mm, 0.65 mm pitch) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | β |
| Operating Temperature | -40C to +85C (industrial, typical) | 0 Β°C to +70 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | EEPROM, second-generation MAX | β |
| Global Clock Pins | 6 | β |
| RoHS Status | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS compliance status] |
| Process Technology | CMOS EEPROM | β |
| Logic Array Blocks | β | 4 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Operating Frequency | β | 100 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Technology | β | EEPROM-based CMOS |
| Programming Interface | β | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Boundary Scan | β | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | β | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |