EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
MPN: EPM7096QC100-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.8 | $980.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
Drop-in alternatives for EPM7096QC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7096LC84-10
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View Datasheet βEPM7096LC84-15
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View Datasheet βEPM7096LC84-7
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View Datasheet βEPM7096LC68-15
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View Datasheet βEPM7096LC68-7
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View Datasheet βEPM7096QC100-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Macrocells | 96 |
| Logic Array Blocks | 4 |
| User I/O Pins | 76 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Technology | EEPROM-based CMOS |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) |
| Package | 100-pin PQFP (R-PQFP-G100, 20Γ14 mm, 0.65 mm pitch) |
| Mounting Type | Surface Mount |
EPM7096QC100-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 2 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 3 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 4 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 5 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 8 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 9 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 10 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 11 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 12 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 13 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 14 | I/O β User I/O pin (Macrocell I/O bank 1) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 17 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 18 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 19 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 20 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 23 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 24 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 25 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 26 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 27 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 30 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 31 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 32 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 33 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 34 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 35 | I/O β User I/O pin (Macrocell I/O bank 2) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 38 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 39 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 40 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 41 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 42 | VCC β +5V supply voltage |
| Pin 43 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 44 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 45 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 46 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 47 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 48 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 51 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 52 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 53 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 54 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 55 | I/O β User I/O pin (Macrocell I/O bank 3) |
| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 58 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 59 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 60 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 61 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 62 | VCC β +5V supply voltage |
| Pin 63 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 64 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 65 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 66 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 67 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 68 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 69 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 70 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 71 | I/O β User I/O pin (Macrocell I/O bank 4) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 74 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 75 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 76 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 77 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 78 | VCC β +5V supply voltage |
| Pin 79 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 80 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 81 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 82 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 83 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 84 | I/O β User I/O pin (Macrocell I/O bank 5) |
| Pin 85 | GND β Ground |
| Pin 86 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 87 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 88 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 89 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 90 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 91 | VCC β +5V supply voltage |
| Pin 92 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 93 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 94 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 95 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 96 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 97 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 98 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 99 | I/O β User I/O pin (Macrocell I/O bank 6) |
| Pin 100 | I/O β User I/O pin (Macrocell I/O bank 6) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7096QC100-10 is suitable for 6 applications: ISA/PCI Bus Address Decoding, Peripheral Glue Logic Replacement, State-Machine Control, Reconfigurable I/O Expansion, Industrial Control Boards, Telecom Backplane Bridging.
ISA/PCI Bus Address Decoding
The EPM7096QC100-10's 10 ns pin-to-pin propagation delay and PCI compliance at -10 speed grade make it well-suited for ISA/PCI bus address decoding in legacy industrial PCs and add-in cards. With 96 macrocells organized into 4 Logic Array Blocks, the device can hold multiple address-decoder windows, chip-select generators, and wait-state logic in a single non-volatile part. The 76 user I/Os easily accommodate full 32-bit address and 16/32-bit data bus multiplexing, while the 5V VCC integrates directly with PCI 5V signaling without level shifters.
Recommended
Peripheral Glue Logic Replacement
The EPM7096QC100-10 is widely used to replace multiple 74-series TTL/CMOS glue-logic chips with a single programmable device, reducing board area and BOM cost. Its 4 Logic Array Blocks and 96 macrocells can implement latches, multiplexers, parity generators, and interrupt controllers that previously required 5 to 10 discrete packages. The 10 ns tPD keeps propagation through the CPLD below one PCI clock cycle, ensuring no setup-time violations on peripheral buses.
Recommended
State-Machine Control
Implementing complex state machines is a classic CPLD use case, and the EPM7096QC100-10's 96 macrocells easily encode FSMs with 16 to 32 states plus output decoding. The deterministic 10 ns tPD enables tight state-transition timing with no jitter from asynchronous routing, while the EEPROM-based non-volatile configuration means the state machine powers up instantly with no external boot PROM. Designers can iterate on the FSM in Altera's legacy MAX+PLUS II toolchain and re-program the device in-circuit via ByteBlaster.
Recommended
Reconfigurable I/O Expansion
The EPM7096QC100-10's 76 user I/O pins make it ideal for reconfigurable I/O expansion in legacy embedded systems where a microcontroller lacks enough pins. The 5V-tolerant I/Os interface directly to 5V peripherals, while the CPLD can implement I2C, SPI, or parallel-bit-banged protocols in firmware-defined logic. Combined with 96 macrocells, one EPM7096QC100-10 can replace an entire I/O-expander ASIC plus its support glue in industrial control boards.
Recommended
Industrial Control Boards
Industrial PLCs, motor controllers, and process-control boards have used the EPM7096QC100-10 for over two decades thanks to its 0β70 Β°C commercial temperature range, robust PQFP-100 footprint, and EEPROM non-volatility. The device hosts encoder interfaces, PWM generators, and fault-logic circuits that benefit from the CPLD's deterministic timing. Long-term field-installed bases in factories continue to require this part for maintenance, even as new designs migrate to MAX II or MAX V.
Recommended
Telecom Backplane Bridging
The EPM7096QC100-10 serves legacy telecom backplanes where it bridges E1/T1 framers, HDLC controllers, and time-slot interchangers through deterministic glue logic. The 100-pin PQFP gives generous I/O headroom for backplane connectors, while 5V VCC and 10 ns tPD meet the timing margins of older TDM buses. PCI-compliance at -10 speed grade ensures interoperability with industry-standard cPCI bridges used in telecom line cards.
Recommended
Recommended Products Summary
Engineering reference data for EPM7096QC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC84-7 | EPM7096LC68-15 | EPM7096LC68-7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 100-pin PQFP | 84-pin PLCC (verify package variant) | 84-pin PLCC (verify package variant) | 84-pin PLCC (verify package variant) | 68-pin PLCC (verify package variant) | 68-pin PLCC (verify package variant) |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 | 96 | 96 | 96 | 96 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 15 ns (+50%) | 7 ns (-30%) | 15 ns (+50%) | 7 ns (-30%) |
| Supply Voltage | 5 V (4.75β5.25 V) | 5 V (4.75β5.25 V) | 5 V (4.75β5.25 V) | 5 V (4.75β5.25 V) | 5 V (4.75β5.25 V) | 5 V (4.75β5.25 V) |
| User I/O Pins | 76 | 68 (PLCC-84) | 68 (PLCC-84) | 68 (PLCC-84) | 52 (PLCC-68) | 52 (PLCC-68) |
| Logic Array Blocks | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster 10 ns tPD speed grade compared to -15 variants (vs EPM7096LC84-15)
- Largest I/O count in the EPM7096 family with 100-pin PQFP (vs EPM7096LC68-15)
- Same MAX 7000 die as the LC family variants β guaranteed architecture compatibility (vs EPM7096LC84-10)
Design Notes
The EPM7096QC100-10 requires a stable +5 V supply within 4.75 V to 5.25 V. Place a 0.1 Β΅F ceramic decoupling capacitor as close as possible to each VCC pin (4 pins: 42, 62, 78, 91) and add a 10 Β΅F tantalum bulk capacitor at the board supply input. Multiple GND pins (6, 15, 21, 28, 36, 49, 56, 72, 85) must all be connected to a low-impedance ground plane to prevent ground-bounce-induced logic errors, especially critical at the -10 ns tPD speed grade.
The PQFP-100 package has a 0.65 mm lead pitch and requires a fine-pitch PCB land pattern compliant with IPC-7351. Use NSMD (non-solder mask defined) pads for better solder joint reliability, and follow JEDEC J-STD-020 MSL handling procedures for any rework. The 20Γ14 mm body has reasonable thermal dissipation for the CMOS core; a continuous ground plane directly under the device acts as a thermal spreader and provides reference for high-speed signals.
Three common pitfalls when designing with the EPM7096QC100-10: (1) confusing the MAX 7000 base variant (this part, parallel programming only) with the MAX 7000S variant (EPM7096S prefix) which adds JTAG ISP β verify the exact MPN suffix before designing the programming interface; (2) exceeding 5.25 V VCC absolute maximum will permanently damage the EEPROM cells; (3) leaving unused I/O pins floating can cause excessive ICC supply current β set unused pins to output-low or input with internal pull-up enabled in the MAX+PLUS II design file.
At 10 ns tPD, the EPM7096QC100-10 drives 5V CMOS signals with rise/fall times around 2β3 ns. Route output traces as 50 Ξ© microstrip or stripline on the ground-plane-referenced PCB to control reflections on long traces. Place series damping resistors (22β33 Ξ©) at outputs driving heavily-loaded buses to reduce ground bounce. For clock inputs, keep traces short and well-isolated from switching I/O to maintain timing margins across the 0β70 Β°C commercial temperature range.
Compliance Information
RoHS, REACH, lead-free and halogen-free status are not explicitly stated in the verified web data for this obsolete Altera/Intel MAX 7000 part. EPM7096QC100-10 was originally released before RoHS became mandatory and many MAX 7000 production lots are non-RoHS β request a compliance certificate from the distributor before using in RoHS-restricted designs.
