EPM7096LC68-7 vs EPM7096QC100-10 Comparación
Comparación detallada lado a lado de EPM7096LC68-7 por Intel y EPM7096QC100-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 ObsoleteComparación de especificaciones
| Parámetro | EPM7096LC68-7 | EPM7096QC100-10 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $7,10 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (EEPROM-based) | — |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 52 | 76 |
| Encapsulado | 68-pin J-Lead PLCC (LC68) | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial, typical) | 0 °C to +70 °C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | EEPROM, second-generation MAX | — |
| Global Clock Pins | 6 | — |
| Estado RoHS | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS compliance status] |
| Process Technology | CMOS EEPROM | — |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | EEPROM-based CMOS |
| Programming Interface | — | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | — | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |