EPM7096LI68-15 vs EPM7096LC68-7 Comparison
Detailed side-by-side comparison of EPM7096LI68-15 by Intel and EPM7096LC68-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7096LI68-15 | EPM7096LC68-7 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | NRND |
| Family | MAX 7000 (second-generation MAX architecture) | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 52 |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Programmable Logic Type | EEPROM-based, in-system programmable (ISP) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Boundary-Scan Test (BST) | Built-in JTAG BST circuitry | — |
| Output Option | Open-drain output option available | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Package | 68-pin PLCC (J-lead, QCCJ) | 68-pin J-Lead PLCC (LC68) |
| Mounting Type | Surface Mount (J-lead) | Surface Mount |
| Speed Grade | -15 (15 ns tPD) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (legacy 5V PLCC) |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Device Type | — | CPLD (EEPROM-based) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature | — | -40C to +85C (industrial, typical) |
| Architecture | — | EEPROM, second-generation MAX |
| Global Clock Pins | — | 6 |