EPM7096LI68-15 vs EPM7096LC68-7 Comparación
Comparación detallada lado a lado de EPM7096LI68-15 por Intel y EPM7096LC68-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7096LI68-15 | EPM7096LC68-7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $9,95 |
| Family | MAX 7000 (second-generation MAX architecture) | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 52 |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Programmable Logic Type | EEPROM-based, in-system programmable (ISP) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Boundary-Scan Test (BST) | Built-in JTAG BST circuitry | — |
| Output Option | Open-drain output option available | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Encapsulado | 68-pin PLCC (J-lead, QCCJ) | 68-pin J-Lead PLCC (LC68) |
| Tipo de montaje | Surface Mount (J-lead) | Surface Mount |
| Speed Grade | -15 (15 ns tPD) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (legacy 5V PLCC) |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Device Type | — | CPLD (EEPROM-based) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Temperatura de funcionamiento | — | -40C to +85C (industrial, typical) |
| Architecture | — | EEPROM, second-generation MAX |
| Global Clock Pins | — | 6 |