EPM7128AETC100-10 vs EPM7128AETC100-7N Comparison
Detailed side-by-side comparison of EPM7128AETC100-10 by Intel and EPM7128AETC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128AETC100-10 | EPM7128AETC100-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | — |
| User I/Os | 84 | 84 |
| Usable Gates | 2.5K | 2,500 |
| Logic Array Blocks (LABs) | 8 | 4 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Program Technology | EEPROM (in-system programmable) | — |
| Package | 100-pin TQFP (ET) | 100-TQFP |
| Operating Temperature | -40C to +85C (commercial/industrial) | 0 C to +70 C (Commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Obsolete (migrate to MAX II or MAX V) | — |
| Macro Cells | — | 128 |
| Propagation Delay (tpd) | — | 7.5 ns |
| Counter Frequency (max) | — | 129.9 MHz |
| Internal Frequency (max) | — | 250 MHz |
| Core Supply Voltage | — | 3.3 V |
| Logic Family | — | CMOS |
| Pin Count | — | 100 |
| Mounting Type | — | Surface Mount |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Process Technology | — | 0.30 µm EEPROM CMOS |