EPM7128AETC100-10N vs EPM7128AETC100-7N Comparison
Detailed side-by-side comparison of EPM7128AETC100-10N by Intel and EPM7128AETC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128AETC100-10N | EPM7128AETC100-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000AE | MAX 7000A |
| Series | EPM7128AE | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | — |
| Usable Gates | 2500 | 2,500 |
| Logic Array Blocks | 16 | — |
| User I/Os | 84 | 84 |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Speed Grade | -10 | — |
| Maximum Frequency | [DATA_NEEDED: maximum toggle frequency] | — |
| Package | TQFP-100 | 100-TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programming | JTAG (IEEE 1149.1) ISP / EEPROM | — |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Lead-Free / RoHS | Yes (N suffix) | — |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM CMOS |
| Architecture | Multiple Array MatriX (MAX) - 2nd generation | — |
| PCI Compliance | Yes (33 MHz, -10 grade per PCI SIG 2.2) | — |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tpd) | — | 7.5 ns |
| Counter Frequency (max) | — | 129.9 MHz |
| Internal Frequency (max) | — | 250 MHz |
| Core Supply Voltage | — | 3.3 V |
| Logic Family | — | CMOS |
| Pin Count | — | 100 |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |