EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
MPN: EPM7128AETC100-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
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View Datasheet →EPM7128AETC100-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000AE |
| Series | EPM7128AE |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2500 |
| Logic Array Blocks | 16 |
| User I/Os | 84 |
| Supply Voltage (Core) | 3.3 V |
| I/O Tolerance | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Speed Grade | -10 |
| Package | TQFP-100 |
| Mounting Type | Surface Mount |
| Programming | JTAG (IEEE 1149.1) ISP / EEPROM |
| Operating Temperature | 0C to +70C (commercial) |
| Lead-Free / RoHS | Yes (N suffix) |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | Yes (33 MHz, -10 grade per PCI SIG 2.2) |
EPM7128AETC100-10N Pin Configuration
| Pin 1 | I/O — User I/O pin (LAB A) |
| Pin 2 | I/O — User I/O pin (LAB A) |
| Pin 3 | I/O — User I/O pin (LAB A) |
| Pin 4 | I/O — User I/O pin (LAB A) |
| Pin 5 | I/O — User I/O pin (LAB A) |
| Pin 6 | I/O — User I/O pin (LAB A) |
| Pin 7 | VCCINT — 3.3V core supply |
| Pin 8 | I/O — User I/O pin (LAB A) |
| Pin 9 | I/O — User I/O pin (LAB A) |
| Pin 10 | I/O — User I/O pin (LAB A) |
| Pin 11 | I/O — User I/O pin (LAB A) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — User I/O pin (LAB A) |
| Pin 14 | I/O — User I/O pin (LAB A) |
| Pin 15 | I/O — User I/O pin (LAB A) |
| Pin 16 | I/O — User I/O pin (LAB A) |
| Pin 17 | I/O — User I/O pin (LAB B) |
| Pin 18 | I/O — User I/O pin (LAB B) |
| Pin 19 | I/O — User I/O pin (LAB B) |
| Pin 20 | I/O — User I/O pin (LAB B) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin (LAB B) |
| Pin 23 | I/O — User I/O pin (LAB B) |
| Pin 24 | I/O — User I/O pin (LAB B) |
| Pin 25 | I/O — User I/O pin (LAB B) |
| Pin 26 | VCCIO — I/O supply voltage |
| Pin 27 | I/O — User I/O pin (LAB B) |
| Pin 28 | I/O — User I/O pin (LAB B) |
| Pin 29 | I/O — User I/O pin (LAB B) |
| Pin 30 | I/O — User I/O pin (LAB C) |
| Pin 31 | I/O — User I/O pin (LAB C) |
| Pin 32 | I/O — User I/O pin (LAB C) |
| Pin 33 | I/O — User I/O pin (LAB C) |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — User I/O pin (LAB C) |
| Pin 36 | I/O — User I/O pin (LAB C) |
| Pin 37 | I/O — User I/O pin (LAB C) |
| Pin 38 | I/O — User I/O pin (LAB C) |
| Pin 39 | I/O — User I/O pin (LAB C) |
| Pin 40 | VCCINT — 3.3V core supply |
| Pin 41 | I/O — User I/O pin (LAB C) |
| Pin 42 | I/O — User I/O pin (LAB C) |
| Pin 43 | I/O — User I/O pin (LAB C) |
| Pin 44 | I/O — User I/O pin (LAB D) |
| Pin 45 | I/O — User I/O pin (LAB D) |
| Pin 46 | I/O — User I/O pin (LAB D) |
| Pin 47 | I/O — User I/O pin (LAB D) |
| Pin 48 | GND — Ground |
| Pin 49 | I/O — User I/O pin (LAB D) |
| Pin 50 | I/O — User I/O pin (LAB D) |
| Pin 51 | I/O — User I/O pin (LAB D) |
| Pin 52 | I/O — User I/O pin (LAB D) |
| Pin 53 | I/O — User I/O pin (LAB D) |
| Pin 54 | VCCIO — I/O supply voltage |
| Pin 55 | I/O — User I/O pin (LAB D) |
| Pin 56 | I/O — User I/O pin (LAB D) |
| Pin 57 | I/O — User I/O pin (LAB E) |
| Pin 58 | I/O — User I/O pin (LAB E) |
| Pin 59 | I/O — User I/O pin (LAB E) |
| Pin 60 | I/O — User I/O pin (LAB E) |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — User I/O pin (LAB E) |
| Pin 63 | I/O — User I/O pin (LAB E) |
| Pin 64 | I/O — User I/O pin (LAB E) |
| Pin 65 | I/O — User I/O pin (LAB E) |
| Pin 66 | I/O — User I/O pin (LAB E) |
| Pin 67 | VCCINT — 3.3V core supply |
| Pin 68 | I/O — User I/O pin (LAB E) |
| Pin 69 | I/O — User I/O pin (LAB F) |
| Pin 70 | I/O — User I/O pin (LAB F) |
| Pin 71 | I/O — User I/O pin (LAB F) |
| Pin 72 | I/O — User I/O pin (LAB F) |
| Pin 73 | GND — Ground |
| Pin 74 | I/O — User I/O pin (LAB F) |
| Pin 75 | I/O — User I/O pin (LAB F) |
| Pin 76 | I/O — User I/O pin (LAB F) |
| Pin 77 | I/O — User I/O pin (LAB F) |
| Pin 78 | I/O — User I/O pin (LAB G) |
| Pin 79 | I/O — User I/O pin (LAB G) |
| Pin 80 | VCCIO — I/O supply voltage |
| Pin 81 | I/O — User I/O pin (LAB G) |
| Pin 82 | I/O — User I/O pin (LAB G) |
| Pin 83 | I/O — User I/O pin (LAB G) |
| Pin 84 | I/O — User I/O pin (LAB G) |
| Pin 85 | I/O — User I/O pin (LAB H) |
| Pin 86 | I/O — User I/O pin (LAB H) |
| Pin 87 | I/O — User I/O pin (LAB H) |
| Pin 88 | GND — Ground |
| Pin 89 | I/O — User I/O pin (LAB H) |
| Pin 90 | I/O — User I/O pin (LAB H) |
| Pin 91 | I/O — User I/O pin (LAB H) |
| Pin 92 | DEV_OE — Device-wide output enable (active low) |
| Pin 93 | DEV_CLRn — Device-wide clear (active low) |
| Pin 94 | GCLK — Global clock input |
| Pin 95 | TDO — JTAG test data output |
| Pin 96 | TMS — JTAG test mode select |
| Pin 97 | TCK — JTAG test clock |
| Pin 98 | TDI — JTAG test data input |
| Pin 99 | I/O — User I/O pin (LAB H) |
| Pin 100 | I/O — User I/O pin (LAB H) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETC100-10N is suitable for 6 applications: PCI Bus Interface Glue Logic, Microprocessor / DSP System Glue Logic, Bus Address Decoding and Mapping, State-Machine Controllers, 5V-to-3.3V Logic Translation Bridges, Telecom and Network Equipment Glue Logic.
PCI Bus Interface Glue Logic
The EPM7128AETC100-10N is widely deployed as PCI bus glue logic between 33 MHz host chipsets and peripheral devices, where its 10 ns pin-to-pin delay and 84 user I/Os are tuned to PCI Local Bus Specification Revision 2.2 timing. The device's JTAG boundary-scan support simplifies PCI compliance testing, while the 5V-tolerant I/O buffers allow direct interface to legacy 5V PCI peripherals. With 128 macrocells, designers can implement address decoding, bus arbitration, command/byte-enable decoding, and parity generation within a single device, eliminating discrete 74-series glue. The MAX 7000AE non-volatile EEPROM technology provides instant-on configuration, eliminating the FPGA-style external boot PROM that would otherwise violate PCI reset sequencing timing.
Recommended
Microprocessor / DSP System Glue Logic
Designers pair the EPM7128AETC100-10N with microprocessors and DSPs to implement custom peripherals, wait-state generators, chip-select decoding, and bus-interface bridges. The CPLD's 84 user I/Os comfortably accommodate 16-bit data buses plus 24-bit address and control signal routing, while 128 macrocells provide ample capacity for address decoding, interrupt control, and FIFOs. Because the part retains its configuration in EEPROM, the host CPU sees a deterministic, instant-on logic block at reset without the boot latency of SRAM-based FPGAs. Industrial PC/104, VME, and embedded SBC designs historically leverage the MAX 7000AE family for this role.
Recommended
Bus Address Decoding and Mapping
The 128 macrocells of the EPM7128AETC100-10N are well-suited to multi-bank address decoding for memory and peripheral subsystems, particularly in 8-bit, 16-bit, and 32-bit microprocessor designs. Designers implement large AND-OR decoder planes that activate chip-select lines based on address ranges and bank-switch logic, replacing dozens of discrete 74LS138/139 decoders. The 10 ns tPD keeps decoded chip-selects stable well within typical microprocessor access-time budgets. JTAG ISP allows late-stage board-bring-up changes to the address map without respinning the PCB.
Recommended
State-Machine Controllers
Industrial control and instrumentation systems use the EPM7128AETC100-10N as a deterministic state-machine controller for sequencing, fault handling, and protocol bridging. Unlike microcontrollers, the CPLD executes state transitions in parallel hardware with sub-10ns response times, making it ideal for sensor-fusion and safety-critical sequencing where interrupt latency would be unacceptable. Each macrocell provides a configurable D/T/JK flip-flop, and 128 macrocells support FSMs with 50+ states plus combinatorial glue logic. The 5V-tolerant I/Os simplify connection to legacy industrial sensors and actuators.
Recommended
5V-to-3.3V Logic Translation Bridges
The EPM7128AETC100-10N operates from a 3.3V core while its I/O buffers are 5V-tolerant, making it ideal as a level-translation bridge between 5V legacy peripherals and 3.3V processors. Designers route 5V signals through the input pins (which tolerate 5V when VCCIO = 3.3V) and produce 3.3V outputs to the host CPU, replacing dedicated level-shifter ICs. With 84 user I/Os, the device can translate 8- or 16-bit data buses plus control signals in a single chip. JTAG ISP enables late-stage configuration of direction-control logic without hardware changes.
Recommended
Telecom and Network Equipment Glue Logic
Telecom and networking platforms historically deployed the EPM7128AETC100-10N for TDM bus arbitration, E1/T1 framing logic, and backplane glue between line cards and switch fabrics. The CPLD's deterministic timing suits SONET/SDH-derived line rates where jitter budgets are tight, while the JTAG boundary-scan simplifies board-level test on densely populated backplanes. With 128 macrocells, designers can implement multiple independent glue-logic functions (clock distribution, frame alignment, alarm generation) in a single device. The commercial 0-70C temperature range suits central-office equipment environments.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC100-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC100-10 | EPM7128AET1100-7 | EPM7128AEFC100-5 | EPM570T100C5N |
|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Family | MAX 7000AE | MAX 7000AE | MAX 7000AE | MAX 7000AE | MAX II |
| Macrocells | 128 | 128 | 128 | 128 | 570 |
| User I/Os | 84 | 84 | 84 | 84 | 76 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 7 ns | 5 ns | 5 ns (MAX II) |
| Supply Voltage (Core) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V (2.5V option) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Active |
| Programming | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / Flash |
Key Differentiators
- Drop-in faster speed-grade option in same TQFP-100 footprint (vs EPM7128AETC100-7)
- Non-volatile EEPROM configuration eliminates boot PROM (vs SRAM-based FPGAs)
- 5V-tolerant I/O on a 3.3V core (vs MAX II EPM570T100C5N)
Design Notes
The EPM7128AETC100-10N requires separate VCCINT (3.3V core) and VCCIO (I/O supply, typically 3.3V) rails. Decouple each VCCINT and VCCIO pin with a 0.1uF ceramic capacitor placed within 5mm of the pin, and add a bulk 10uF tantalum or ceramic capacitor near each supply pin group. Power-up sequencing is not critical because internal POR circuitry holds the device in reset until VCCINT stabilizes. The 'N' suffix indicates lead-free (Pb-free) matte-tin finish compatible with lead-free reflow profiles up to 260C peak.
Route JTAG signals (TCK, TMS, TDI, TDO) with characteristic impedance of 50 ohms and keep them short to minimize reflections. Place a 10kohm pull-up on TCK and TMS to ensure defined logic levels during cable disconnect; TDO is high-impedance when not shifting and does not require a pull-up. Reserve a JTAG header or test-pad access on the PCB even if programming is performed only at board assembly - field firmware updates are common. Keep global clock (GCLK) traces short and routed away from high-speed I/O to minimize crosstalk into the clock domain.
A common pitfall is assuming the 5V-tolerant I/O outputs 5V levels - the I/O buffers drive to VCCIO (typically 3.3V), not 5V. To interface with 5V logic inputs, the EPM7128AE outputs can drive 5V CMOS inputs if VCCIO = 3.3V and the receiver has TTL-compatible thresholds, but not true 5V CMOS levels. Another pitfall is neglecting the in-system programming cycle time (typically 1-3 seconds via JTAG) - production test fixtures must allow this delay. Finally, verify the Quartus II software version supports the specific -10 speed grade before compiling legacy designs, because some newer Quartus releases deprecate older MAX device timing models.
The TQFP-100 package has a typical theta_JA of approximately 50 C/W in still air, allowing continuous operation up to about 0.8W dissipation at 25C ambient. For designs with high toggle rates across all 84 I/Os, estimate dynamic power at approximately P_dynamic = C_load * VCCIO^2 * f * N, where N is the number of switching outputs; for typical 25 MHz operation on 50 outputs with 30pF load this is approximately 0.4W. Add copper thermal relief under the TQFP-100 package on inner PCB layers if the design operates near the upper commercial temperature limit (70C).
Compliance Information
Lead-free / Pb-free matte-tin finish per the N suffix. RoHS compliant per distributor product pages. AEC-Q100 not applicable - this is a commercial-grade CPLD, not an automotive-qualified part. Operating temperature range is 0C to +70C commercial.
