EPM7128AETC100-5N vs EPM7128ATC100-7F Comparison
Detailed side-by-side comparison of EPM7128AETC100-5N by Intel and EPM7128ATC100-7F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N ✓ ActiveAltera
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F NrndSpecification Comparison
| Parameter | EPM7128AETC100-5N | EPM7128ATC100-7F |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | NRND |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | — |
| User I/Os | 84 | — |
| Logic Gates (typical) | 2,500 | — |
| Pin-to-Pin Logic Delay (tPD) | 5 ns | — |
| Maximum Operating Frequency | 192.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) | — |
| Programmable Logic Type | EEPROM-based, in-system programmable | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) | — |
| Package | 100-pin TQFP | 100-pin TQFP (14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Device | — | EPM7128A |
| Logic Elements / Macrocells | — | 128 macrocells |
| Logic Array Blocks (LABs) | — | 8 |
| Usable Gates | — | 2.5K |
| User I/O Pins | — | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 116.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V (nominal 3.3 V) |
| I/O Voltage | — | 2.5 V / 3.3 V (MultiVolt) |
| Programmable Type | — | EEPROM (in-system programmable, non-volatile) |
| JTAG Support | — | IEEE Std 1149.1 boundary-scan + ISP |
| Process Technology | — | CMOS, EEPROM configuration |