EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
MPN: EPM7128ATC100-7F β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM7128ATC100-7F β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128ATC100-10
β Drop-Inβ In Stock
$4.95 / Unit
View Datasheet βEPM7128AETI100-7
β Drop-Inβ In Stock
$30.1 / Unit
View Datasheet βEPM7128AETC100-7N
β Drop-Inβ In Stock
$31.8 / Unit
View Datasheet βEPM7128AETC100-10N
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128AETC100-5N
β Drop-Inβ In Stock
$6.85 / Unit
View Datasheet βEPM7128AETC100-10
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPM7128ATC100-7F Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device | EPM7128A |
| Logic Elements / Macrocells | 128 macrocells |
| Logic Array Blocks (LABs) | 8 |
| Usable Gates | 2.5K |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Internal Frequency (fMAX) | 116.3 MHz |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) |
| Programmable Type | EEPROM (in-system programmable, non-volatile) |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP |
| Package | 100-pin TQFP (14x14 mm) |
| Operating Temperature | -40C to +85C (industrial) |
| Process Technology | CMOS, EEPROM configuration |
| Mounting Type | Surface Mount |
EPM7128ATC100-7F Pin Configuration
| Pin 1 | I/O β User I/O (Bank 1) |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | I/O β User I/O (Bank 1) |
| Pin 7 | VCCINT β 3.3V core supply |
| Pin 8 | I/O β User I/O (Bank 1) |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O (Bank 1) |
| Pin 12 | I/O β User I/O (Bank 1) |
| Pin 13 | I/O β User I/O (Bank 1) |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | I/O β User I/O (Bank 1) |
| Pin 18 | I/O β User I/O (Bank 1) |
| Pin 19 | I/O β User I/O (Bank 1) |
| Pin 20 | I/O β User I/O (Bank 1) |
| Pin 21 | VCCIO1 β I/O Bank 1 supply (2.5V/3.3V) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O (Bank 1) |
| Pin 24 | I/O β User I/O (Bank 1) |
| Pin 25 | I/O β User I/O (Bank 1) |
| Pin 26 | I/O β User I/O (Bank 2) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | I/O β User I/O (Bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O (Bank 2) |
| Pin 32 | I/O β User I/O (Bank 2) |
| Pin 33 | I/O β User I/O (Bank 2) |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | I/O β User I/O (Bank 2) |
| Pin 37 | VCCIO2 β I/O Bank 2 supply (2.5V/3.3V) |
| Pin 38 | I/O β User I/O (Bank 2) |
| Pin 39 | I/O β User I/O (Bank 2) |
| Pin 40 | I/O β User I/O (Bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O (Bank 2) |
| Pin 43 | I/O β User I/O (Bank 2) |
| Pin 44 | I/O β User I/O (Bank 2) |
| Pin 45 | I/O β User I/O (Bank 2) |
| Pin 46 | I/O β User I/O (Bank 3) |
| Pin 47 | I/O β User I/O (Bank 3) |
| Pin 48 | I/O β User I/O (Bank 3) |
| Pin 49 | I/O β User I/O (Bank 3) |
| Pin 50 | I/O β User I/O (Bank 3) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O (Bank 3) |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | I/O β User I/O (Bank 3) |
| Pin 55 | I/O β User I/O (Bank 3) |
| Pin 56 | VCCIO3 β I/O Bank 3 supply (2.5V/3.3V) |
| Pin 57 | I/O β User I/O (Bank 3) |
| Pin 58 | I/O β User I/O (Bank 3) |
| Pin 59 | I/O β User I/O (Bank 3) |
| Pin 60 | I/O β User I/O (Bank 3) |
| Pin 61 | I/O β User I/O (Bank 3) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O (Bank 3) |
| Pin 64 | I/O β User I/O (Bank 3) |
| Pin 65 | I/O β User I/O (Bank 3) |
| Pin 66 | I/O β User I/O (Bank 3) |
| Pin 67 | I/O β User I/O (Bank 4) |
| Pin 68 | I/O β User I/O (Bank 4) |
| Pin 69 | I/O β User I/O (Bank 4) |
| Pin 70 | I/O β User I/O (Bank 4) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O (Bank 4) |
| Pin 73 | I/O β User I/O (Bank 4) |
| Pin 74 | I/O β User I/O (Bank 4) |
| Pin 75 | I/O β User I/O (Bank 4) |
| Pin 76 | VCCIO4 β I/O Bank 4 supply (2.5V/3.3V) |
| Pin 77 | I/O β User I/O (Bank 4) |
| Pin 78 | I/O β User I/O (Bank 4) |
| Pin 79 | I/O β User I/O (Bank 4) |
| Pin 80 | I/O β User I/O (Bank 4) |
| Pin 81 | I/O β User I/O (Bank 4) |
| Pin 82 | I/O β User I/O (Bank 4) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O (Bank 4) |
| Pin 85 | I/O β User I/O (Bank 4) |
| Pin 86 | I/O β User I/O (Bank 4) |
| Pin 87 | I/O β User I/O (Bank 4) |
| Pin 88 | I/O β User I/O (Bank 4) |
| Pin 89 | I/O β User I/O (Bank 4) |
| Pin 90 | I/O β User I/O (Bank 4) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O (Bank 4) |
| Pin 93 | I/O β User I/O (Bank 4) |
| Pin 94 | TDO β JTAG Test Data Out |
| Pin 95 | I/O β User I/O (Bank 4) |
| Pin 96 | I/O β User I/O (Bank 4) |
| Pin 97 | I/O β User I/O (Bank 1) |
| Pin 98 | I/O β User I/O (Bank 1) |
| Pin 99 | I/O β User I/O (Bank 1) |
| Pin 100 | I/O β User I/O (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ATC100-7F is suitable for 6 applications: PCI / ISA Bus Glue Logic, Address Decoding & Chip-Select Generation, State Machine & Sequencer Controller, Legacy 5V to 3.3V Bus Translator, Power-Sequencing & Reset Logic, Asynchronous Interface Bridging (UART / SPI / I2C).
PCI / ISA Bus Glue Logic
The EPM7128ATC100-7F is a strong fit for PCI/ISA bus glue logic where deterministic sub-10 ns timing is mandatory: address decoding, chip-select generation, wait-state insertion, and bus arbitration all benefit from the part's 7.5 ns pin-to-pin propagation delay and 116.3 MHz fMAX. With 128 macrocells and 84+ user I/Os, it can replace multiple 74-series glue-logic packages on legacy ISA cards while reducing board area and BOM count. The 3.3V core with 5V-tolerant MultiVolt I/O lets it bridge directly to older 5V peripherals through a simple series resistor, easing migration of legacy industrial PCs without redesigning the entire backplane.
Recommended
Address Decoding & Chip-Select Generation
Use the EPM7128ATC100-7F as a centralized address decoder to generate chip-select, output-enable, and write-enable signals for memory banks and peripherals sharing a common bus. Each macrocell can implement a wide product-term AND/OR decode, and the device's 100 user I/Os comfortably handle up to a 24-bit address plus 8-bit chip-select fan-out. The 7.5 ns tPD keeps decoded strobes inside a single 33 MHz PCI cycle (30 ns period), eliminating metastability risk and removing the need for an external decoder PAL. Engineers can revision-fix decode bugs in seconds by recompiling the EEPROM bitstream via JTAG.
Recommended
State Machine & Sequencer Controller
The EPM7128ATC100-7F excels as a finite state machine controller for power-sequencer, motor-control, or industrial-automation logic. Each of its 128 macrocells contains a flip-flop and dedicated product-term allocation logic, allowing up to 128 registered states per device with combinational glue logic on the same die. The non-volatile EEPROM configuration means the sequencer boots in microseconds at power-on - critical for fail-safe controllers where an SRAM-based FPGA would otherwise need an external boot PROM and add tens of milliseconds to startup. Quartus II synthesis of legacy .tdf or .vhd state-machine code yields predictable timing reports that match silicon behavior within one tPD.
Recommended
Legacy 5V to 3.3V Bus Translator
The EPM7128ATC100-7F's MultiVolt I/O makes it a practical bridge between legacy 5V peripherals and modern 3.3V processors or ASICs. Each I/O bank can be independently powered at 2.5V or 3.3V, and the inputs tolerate 5V signals through a 100 ohm series resistor, eliminating dedicated level-shifter ICs. The CPLD can also implement bidirectional bus switches and direction-control logic in the same device, reducing the bill of materials on mixed-voltage adapter boards. With 84+ I/Os available, a single EPM7128ATC100-7F can translate a full 8/16/32-bit data bus plus handshaking signals in one package.
Recommended
Power-Sequencing & Reset Logic
Power-sequencing logic for multi-rail systems is a natural fit for the EPM7128ATC100-7F: instant-on EEPROM configuration means rail-ordering signals are valid within microseconds of VCCINT reaching regulation, without the boot delay of an SRAM FPGA. The 7.5 ns tPD supports fast Power-Good cascades and programmable watchdog timers for FPGAs, ASICs, and microprocessors that require specific rail-up/down ordering per their datasheets. Built-in JTAG (IEEE 1149.1) boundary-scan lets production test verify every power-sequencing net is correctly wired before the rest of the board is powered up.
Recommended
Asynchronous Interface Bridging (UART / SPI / I2C)
Bridging asynchronous peripherals to a host bus is a classic CPLD application, and the EPM7128ATC100-7F brings 128 macrocells and 100 user I/Os to handle multi-channel UART, SPI master/slave, and I2C controller/slave bridges in a single device. Each macrocell implements the bit-banging or state-machine logic with deterministic sub-10 ns timing, which is critical when emulating an I2C master at 400 kHz Fast-mode or driving multiple SPI slaves with precise chip-select skew. Compared with bit-banging on a microcontroller, the CPLD approach offloads deterministic real-time work from the host CPU and runs in parallel without scheduler jitter.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ATC100-7F β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128ATC100-10 | EPM7128AETI100-7 | EPM7128AETC100-7N | EPM7128AETC100-5N |
|---|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns | 7.5 ns | 7.5 ns | 5 ns |
| Internal Frequency (fMAX) | 116.3 MHz | 100 MHz (est.) | 116.3 MHz | 116.3 MHz | 147 MHz (est.) |
| Core Voltage | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V | 3.0V - 3.6V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C (I suffix) | -40C to +85C | -40C to +85C |
| Lead-Free Finish | Yes (F suffix) | Optional (N suffix variants exist) | Optional | Yes (N suffix) | Yes (N suffix) |
Key Differentiators
- 7.5 ns grade with industrial-temp 'I' suffix variant available (vs EPM7128ATC100-10)
- Lead-free (F suffix) assembly compliance (vs EPM7128ATC100-7 (leaded))
- Same-package 5 ns grade upgrade path (vs EPM7128AETC100-5N)
Design Notes
The EPM7128ATC100-7F requires a 3.0V-3.6V core supply on VCCINT plus one or more 2.5V/3.3V supplies on the VCCIO bank pins (VCCIO1-VCCIO4). Estimated: at 100% utilization with all 128 macrocells toggling at 116 MHz, the device draws roughly 250-400 mA from VCCINT, so place 0.1 uF X7R decoupling caps within 5 mm of every VCCINT/VCCIO pin and a single 10 uF bulk tantalum near the package. Sharing a 3.3V rail with a noisy switching converter is acceptable for logic but adds jitter to clock nets - keep a ferrite bead between switching and CPLD supplies.
Route JTAG signals (TCK, TMS, TDI, TDO) as a 4-wire daisy-chain with optional TRST, keeping total stub length under 25 mm and using 10 kohm pull-ups on TMS, TDI, and TRST to prevent accidental JTAG state-machine entry at power-up. The 100-pin TQFP has 0.5 mm pitch, which is hand-solderable with a fine tip but requires a hot-plate or reflow profile (ramp 1-2 C/s, peak 245 C, 60 s above 220 C) for reliable assembly. Decoupling caps should sit on the same side as the CPLD to minimize loop inductance.
Common pitfalls with the EPM7128ATC100-7F include: (1) forgetting the JTAG chain reservation when board space is tight - all four JTAG pins must remain accessible for ISP; (2) mixing 5V inputs directly into MultiVolt I/O without a series resistor, which overstresses the input clamp diodes; (3) using the device outside Quartus MAX+PLUS II legacy support, since newer Quartus versions dropped MAX 7000A synthesis - confirm tool support before starting a new design. Also note the part is NRD (Not Recommended for New Designs), so plan a migration path to MAX II or MAX V for new product development.
Compliance Information
F suffix indicates lead-free terminal finish per industry convention. RoHS/REACH compliance not explicitly stated in verified web data - check Altera/Intel environmental documentation before qualifying for new designs.
