EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
MPN: EPM7128AETC100-5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.2 | $11.20 |
| 10 | $10.08 | $100.80 |
| 100 | $8.95 | $895.00 |
| 500 | $7.95 | $3,975.00 |
| 1,000 | $6.85 | $6,850.00 |
Drop-in alternatives for EPM7128AETC100-5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC100-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETC100-10N
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128AETC100-5
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETC100-10
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPM7128AETC100-5N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 |
| User I/Os | 84 |
| Logic Gates (typical) | 2,500 |
| Pin-to-Pin Logic Delay (tPD) | 5 ns |
| Maximum Operating Frequency | 192.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) |
| Programmable Logic Type | EEPROM-based, in-system programmable |
| Programming Interface | JTAG (IEEE Std. 1149.1) |
| Package | 100-pin TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Compliant |
EPM7128AETC100-5N Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell 84) |
| Pin 2 | I/O β User I/O pin (macrocell 83) |
| Pin 3 | I/O β User I/O pin (macrocell 82) |
| Pin 4 | I/O β User I/O pin (macrocell 81) |
| Pin 5 | I/O β User I/O pin (macrocell 80) |
| Pin 6 | I/O β User I/O pin (macrocell 79) |
| Pin 7 | I/O β User I/O pin (macrocell 78) |
| Pin 8 | I/O β User I/O pin (macrocell 77) |
| Pin 9 | VCCINT β Core supply voltage (3.3 V) |
| Pin 10 | I/O β User I/O pin (macrocell 76) |
| Pin 11 | I/O β User I/O pin (macrocell 75) |
| Pin 12 | I/O β User I/O pin (macrocell 74) |
| Pin 13 | I/O β User I/O pin (macrocell 73) |
| Pin 14 | I/O β User I/O pin (macrocell 72) |
| Pin 15 | I/O β User I/O pin (macrocell 71) |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β User I/O pin (macrocell 70) |
| Pin 18 | I/O β User I/O pin (macrocell 69) |
| Pin 19 | I/O β User I/O pin (macrocell 68) |
| Pin 20 | I/O β User I/O pin (macrocell 67) |
| Pin 21 | I/O β User I/O pin (macrocell 66) |
| Pin 22 | I/O β User I/O pin (macrocell 65) |
| Pin 23 | I/O β User I/O pin (macrocell 64) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin (macrocell 63) |
| Pin 26 | I/O β User I/O pin (macrocell 62) |
| Pin 27 | I/O β User I/O pin (macrocell 61) |
| Pin 28 | I/O β User I/O pin (macrocell 60) |
| Pin 29 | I/O β User I/O pin (macrocell 59) |
| Pin 30 | I/O β User I/O pin (macrocell 58) |
| Pin 31 | I/O β User I/O pin (macrocell 57) |
| Pin 32 | VCCIO β I/O bank supply voltage (3.3 V or 2.5 V) |
| Pin 33 | I/O β User I/O pin (macrocell 56) |
| Pin 34 | I/O β User I/O pin (macrocell 55) |
| Pin 35 | I/O β User I/O pin (macrocell 54) |
| Pin 36 | I/O β User I/O pin (macrocell 53) |
| Pin 37 | I/O β User I/O pin (macrocell 52) |
| Pin 38 | I/O β User I/O pin (macrocell 51) |
| Pin 39 | I/O β User I/O pin (macrocell 50) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (macrocell 49) |
| Pin 42 | I/O β User I/O pin (macrocell 48) |
| Pin 43 | I/O β User I/O pin (macrocell 47) |
| Pin 44 | I/O β User I/O pin (macrocell 46) |
| Pin 45 | I/O β User I/O pin (macrocell 45) |
| Pin 46 | I/O β User I/O pin (macrocell 44) |
| Pin 47 | I/O β User I/O pin (macrocell 43) |
| Pin 48 | VCCINT β Core supply voltage (3.3 V) |
| Pin 49 | I/O β User I/O pin (macrocell 42) |
| Pin 50 | I/O β User I/O pin (macrocell 41) |
| Pin 51 | I/O β User I/O pin (macrocell 40) |
| Pin 52 | I/O β User I/O pin (macrocell 39) |
| Pin 53 | I/O β User I/O pin (macrocell 38) |
| Pin 54 | I/O β User I/O pin (macrocell 37) |
| Pin 55 | I/O β User I/O pin (macrocell 36) |
| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O pin (macrocell 35) |
| Pin 58 | I/O β User I/O pin (macrocell 34) |
| Pin 59 | I/O β User I/O pin (macrocell 33) |
| Pin 60 | I/O β User I/O pin (macrocell 32) |
| Pin 61 | I/O β User I/O pin (macrocell 31) |
| Pin 62 | I/O β User I/O pin (macrocell 30) |
| Pin 63 | I/O β User I/O pin (macrocell 29) |
| Pin 64 | VCCIO β I/O bank supply voltage (3.3 V or 2.5 V) |
| Pin 65 | I/O β User I/O pin (macrocell 28) |
| Pin 66 | I/O β User I/O pin (macrocell 27) |
| Pin 67 | I/O β User I/O pin (macrocell 26) |
| Pin 68 | I/O β User I/O pin (macrocell 25) |
| Pin 69 | I/O β User I/O pin (macrocell 24) |
| Pin 70 | I/O β User I/O pin (macrocell 23) |
| Pin 71 | I/O β User I/O pin (macrocell 22) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin (macrocell 21) |
| Pin 74 | I/O β User I/O pin (macrocell 20) |
| Pin 75 | I/O β User I/O pin (macrocell 19) |
| Pin 76 | I/O β User I/O pin (macrocell 18) |
| Pin 77 | I/O β User I/O pin (macrocell 17) |
| Pin 78 | I/O β User I/O pin (macrocell 16) |
| Pin 79 | I/O β User I/O pin (macrocell 15) |
| Pin 80 | VCCINT β Core supply voltage (3.3 V) |
| Pin 81 | I/O β User I/O pin (macrocell 14) |
| Pin 82 | I/O β User I/O pin (macrocell 13) |
| Pin 83 | I/O β User I/O pin (macrocell 12) |
| Pin 84 | I/O β User I/O pin (macrocell 11) |
| Pin 85 | I/O β User I/O pin (macrocell 10) |
| Pin 86 | I/O β User I/O pin (macrocell 9) |
| Pin 87 | I/O β User I/O pin (macrocell 8) |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β User I/O pin (macrocell 7) |
| Pin 90 | I/O β User I/O pin (macrocell 6) |
| Pin 91 | I/O β User I/O pin (macrocell 5) |
| Pin 92 | I/O β User I/O pin (macrocell 4) |
| Pin 93 | I/O β User I/O pin (macrocell 3) |
| Pin 94 | I/O β User I/O pin (macrocell 2) |
| Pin 95 | I/O β User I/O pin (macrocell 1) |
| Pin 96 | VCCIO β I/O bank supply voltage (3.3 V or 2.5 V) |
| Pin 97 | TDI β JTAG Test Data In |
| Pin 98 | TMS β JTAG Test Mode Select |
| Pin 99 | TCK β JTAG Test Clock |
| Pin 100 | TDO β JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETC100-5N is suitable for 6 applications: Industrial Glue Logic and Address Decoding, 5V to 3.3V Bus Voltage Translation Bridge, Embedded Peripheral Control and State Machines, Communications Backplane Glue and TDM Switching, PCI Bus Interface and Arbiter Logic, Legacy System Modernization and I/O Expansion.
Industrial Glue Logic and Address Decoding
The EPM7128AETC100-5N is widely used as address-decoding glue logic in 8/16/32-bit microprocessor and DSP systems, where its 5 ns tPD and 84 user I/Os can replace stacks of 74LS/74HC discrete decoder gates. The 128 macrocells can implement multiple independent chip-select functions, register-based state machines, and wait-state generators in a single non-volatile device that powers up instantly from on-chip EEPROM - critical for industrial PLC backplanes where predictable boot behavior is mandatory. Its 5V-tolerant inputs (when VCCIO = 3.3V) allow direct interfacing to legacy 5V peripheral buses without external level shifters, and the JTAG ISP support enables field firmware updates without removing the board from service.
Recommended
5V to 3.3V Bus Voltage Translation Bridge
The EPM7128AETC100-5N operates as a bidirectional voltage-translation bridge between 5V legacy microcontrollers and 3.3V modern peripherals, exploiting its MultiVolt I/O architecture where VCCIO can be tied to 3.3V while inputs tolerate 5V signals. With 84 I/Os and 5 ns propagation delay, it can buffer an entire 16-bit data bus plus address and control signals in a single chip, replacing discrete bus-switch ICs (e.g., 74LVTH245) with programmable direction control per bit. The 100-pin TQFP footprint gives ample headroom for 32-bit datapaths and interrupt steering, and the JTAG ISP allows designers to redefine the direction map in the field.
Recommended
Embedded Peripheral Control and State Machines
Designers use the EPM7128AETC100-5N to implement custom peripheral controllers, FIFO hand-shaking logic, and complex multi-state control sequences that would otherwise require a small FPGA or a large discrete state-machine board. The 128 macrocells and 192.3 MHz Fmax comfortably handle encoder quadrature decoding, stepper-motor pulse trains, and PWM generation at industrial switching frequencies. Deterministic 5 ns timing paths allow the part to replace small PAL/GAL arrays and 22V10 devices while offering more I/O and instant-on EEPROM configuration - no boot PROM or external flash required, which reduces PCB area and BOM cost.
Recommended
Communications Backplane Glue and TDM Switching
In telecom and datacom backplanes, the EPM7128AETC100-5N serves as a programmable TDM (Time-Division Multiplexing) switch, frame-alignment engine, and clock-distribution buffer, where the 5 ns propagation delay is fast enough to retime E1/T1 or JESD204B-aligned data without adding measurable jitter. The 84 I/Os handle multiple serial streams plus framing overhead, while the four I/O banks allow direct interfacing to 3.3V PHY chips and 2.5V line-interface units from a single CPLD. In-system programmability lets the same hardware platform be repurposed across product variants by simply reloading the EEPROM image via JTAG.
Recommended
PCI Bus Interface and Arbiter Logic
The EPM7128AETC100-5N implements PCI bus target devices, bus arbiters, and configuration-space registers in legacy 33 MHz PCI add-in cards. When VCCIO is tied to 3.3V the I/O drivers meet the PCI 3.3V signalling standard directly, and the 128 macrocells can hold the full PCI target state machine plus interrupt acknowledge and parity logic. Compared to a dedicated PCI interface ASIC, the CPLD offers full design flexibility and field firmware updates via JTAG, while the 5 ns tPD comfortably meets the 33 MHz PCI clock-period budget of 30 ns across the CPLD's combinational paths.
Recommended
Legacy System Modernization and I/O Expansion
When modernizing 8051, 68k, or other legacy CPU platforms, designers drop in the EPM7128AETC100-5N to add USB, SD-card, or LCD interfaces that the original processor could not natively drive. The 84 I/Os can host an 8/16-bit parallel bus plus chip-select, read/write, and interrupt lines for multiple peripherals, while the EEPROM-based configuration means the firmware lives with the hardware. The 100-pin TQFP footprint and 5V-tolerant inputs ease retrofitting into older 5V-system boards, and the JTAG port allows in-circuit reprogramming during bring-up.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC100-5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC100-7 | EPM7128AETC100-10N | EPM7128AETC100-5 | EPM7128AELC84-10N |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | PLCC-84 - different |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Pin-to-Pin Delay (tPD) | 5 ns | 7 ns | 10 ns | 5 ns | 10 ns |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 84 | 84 | 84 | 84 | 68 |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| RoHS / Pb-free | Yes (N suffix) | [DATA_NEEDED] | Yes | No (non-N) | Yes |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
Key Differentiators
- Fastest speed grade in the EPM7128AE TQFP-100 family (vs EPM7128AETC100-7)
- Same die, RoHS-compliant ("N" suffix) production material (vs EPM7128AETC100-5)
- TQFP-100 footprint with 84 user I/Os (vs EPM7128AELC84-10N)
Design Notes
According to the Altera datasheet Operating Requirements section, VCC must rise monotonically for EPM7128A and EPM7256A devices - a non-monotonic ramp can corrupt the on-chip EEPROM configuration or trigger spurious JTAG operations. Use a supervisor IC or a well-decoupled linear regulator with controlled rise time between 1 ms and 100 ms; avoid slow RC ramps longer than 100 ms or pulsed / stepped power-up sequences. Decouple each VCCINT and VCCIO pin with a 0.1 uF X7R ceramic placed within 5 mm of the lead, plus a bulk 10 uF tantalum or ceramic near the device.
The MAX 7000A datasheet specifies minimum DC input voltage of -0.5 V; during transitions inputs may undershoot to -2.0 V only for input currents less than 100 mA and periods shorter than 20 ns. Add a 33 ohm series resistor and a clamp diode to GND on any input that is hot-plugged or that connects to a long PCB trace to prevent EOS damage. Also note that VCCIO below 3.0 V incurs the slower tOD2 delay instead of tOD1 - design timing margins accordingly if you operate VCCIO at 2.5 V.
The 100-pin TQFP package has multiple VCCINT (pins 9, 48, 80) and VCCIO (pins 32, 64, 96) pads that must each be decoupled separately - do not share a single decoupling capacitor across pins. Route JTAG signals (TDI/TDO/TMS/TCK) as a short daisy chain with 33 ohm series termination if the cable to the programming header exceeds 50 mm; floating TMS at power-up can place the TAP controller in an undefined state and block ISP. Keep the JTAG header within 100 mm of the CPLD to avoid signal-integrity issues with the long TCK rise time.
When using the EPM7128AETC100-5N as a 5V-to-3.3V level shifter with VCCIO at 3.3 V, the inputs are 5V tolerant but the outputs swing only to 3.3 V - confirm that all downstream receivers meet VIH at 3.3 V CMOS levels (typically 2.0 V minimum). For high-speed (>50 MHz) outputs add 22-33 ohm series damping resistors to control ringing on long PCB traces; the CPLD output edge rates are sub-2 ns and will otherwise over-shoot on unterminated lines. Avoid using the same I/O bank for both 3.3 V and 2.5 V signalling because the bank VCCIO sets the drive level for the entire bank.
Compliance Information
RoHS compliance is implied by the "N" suffix in the part number, per Altera/Intel legacy datasheet naming. AEC-Q100 is not applicable as this is a commercial-grade CPLD; an industrial-grade version is not catalogued. REACH compliance assumed by major distributors (Heisener, DigiKey) but not explicitly stated on the datasheet excerpts provided.
