EPM7128AETC100-7N vs EPM7128STC100-6N Comparison
Detailed side-by-side comparison of EPM7128AETC100-7N by Altera and EPM7128STC100-6N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteSpecification Comparison
| Parameter | EPM7128AETC100-7N | EPM7128STC100-6N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tpd) | 7.5 ns | — |
| Counter Frequency (max) | 129.9 MHz | — |
| Internal Frequency (max) | 250 MHz | — |
| Core Supply Voltage | 3.3 V | — |
| Logic Family | CMOS | CMOS |
| Pin Count | 100 | — |
| Package | 100-TQFP | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (Commercial) | 0C to +70C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-Compliant (lead-bearing package) |
| Process Technology | 0.30 µm EEPROM CMOS | CMOS EEPROM |
| Number of Pins | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |