EPM7128AETC144-7N vs EPM7128AETC144-7 Comparison
Detailed side-by-side comparison of EPM7128AETC144-7N by Altera and EPM7128AETC144-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-7N
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N β ActiveIntel
EPM7128AETC144-7
EPM7128AETC144-7 - 128-Macrocell 7.5ns MAX 7000A CPLD | Intel
EPM7128AETC144-7 ObsoleteSpecification Comparison
| Parameter | EPM7128AETC144-7N | EPM7128AETC144-7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $39.82 | $16.40 |
| Family | MAX 7000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 2500 (2.5K gates) | β |
| Macro Cells | 128 | β |
| User I/Os | 36 (in 144-pin TQFP) | β |
| Maximum Operating Frequency | 129.9 MHz | 129.9 MHz |
| Pin-to-Pin Delay | 7.5 ns | β |
| Propagation Delay (tpd) | 7.5 ns | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V |
| Process Technology | CMOS, EEPROM-based | CMOS |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Package | 144-pin TQFP | 144-pin TQFP (20x20 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | β |
| Series | β | MAX 7000A |
| Programmable Type | β | In-System Programmable (ISP), EEPROM |
| Number of Macrocells | β | 128 |
| Number of Logic Array Blocks (LABs) | β | 8 |
| Number of Usable Gates | β | 2,500 |
| Number of I/Os | β | 100 |
| Propagation Delay (tPD) Max | β | 7.5 ns |
| I/O Voltage (MultiVolt) | β | 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | β | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) |
| Configuration Memory | β | EEPROM, non-volatile |
| ISP Endurance | β | 100 cycles typical per macrocell |