EPM7128AETI100-7 vs EPM7128AETC100-10N Comparison
Detailed side-by-side comparison of EPM7128AETI100-7 by Altera and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteIntel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128AETI100-7 | EPM7128AETC100-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $30.10 | $9.95 |
| Family | MAX 7000A | MAX 7000AE |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| User I/Os | 84 | 84 |
| Logic Blocks (LABs) | 8 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Counter Frequency | 129.9 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | β |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | β |
| Global Clock Inputs | 4 dedicated | β |
| Package | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | TQFP-100 |
| Operating Temperature | -40 C to +85 C (Industrial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: confirm RoHS for non-N suffix] | β |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | β |
| Series | β | EPM7128AE |
| Logic Array Blocks | β | 16 |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Tolerance | β | 5.0 V tolerant |
| Speed Grade | β | -10 |
| Maximum Frequency | β | [DATA_NEEDED: maximum toggle frequency] |
| Programming | β | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Process Technology | β | CMOS EEPROM |
| Architecture | β | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | β | Yes (33 MHz, -10 grade per PCI SIG 2.2) |