EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
MPN: EPM7128AETI100-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $46.25 | $46.25 |
| 10 | $41.63 | $416.30 |
| 100 | $37.21 | $3,721.00 |
| 500 | $33.5 | $16,750.00 |
| 1,000 | $30.1 | $30,100.00 |
Drop-in alternatives for EPM7128AETI100-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETI100-7N
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View Datasheet βEPM7128AETC100-7N
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View Datasheet βEPM7128AETC100-7N
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View Datasheet βEPM7128AETC100-10N
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$9.95 / Unit
View Datasheet βEPM7128AET1100-7
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View Datasheet βEPM7128AETI100-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 84 |
| Logic Blocks (LABs) | 8 |
| Pin-to-Pin Delay (tPD) | 7.5 ns |
| Maximum Counter Frequency | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | 3.3 V |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | 4 dedicated |
| Package | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Mounting Type | Surface Mount |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |
EPM7128AETI100-7 Pin Configuration
| Pin 1 | I/O β User I/O pin (Bank 1) |
| Pin 2 | I/O β User I/O pin (Bank 1) |
| Pin 3 | I/O β User I/O pin (Bank 1) |
| Pin 4 | I/O β User I/O pin (Bank 1) |
| Pin 5 | I/O β User I/O pin (Bank 1) |
| Pin 6 | I/O β User I/O pin (Bank 1) |
| Pin 7 | I/O β User I/O pin (Bank 1) |
| Pin 8 | I/O β User I/O pin (Bank 1) |
| Pin 9 | I/O β User I/O pin (Bank 1) |
| Pin 10 | I/O β User I/O pin (Bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (Bank 1) |
| Pin 13 | I/O β User I/O pin (Bank 1) |
| Pin 14 | I/O β User I/O pin (Bank 1) |
| Pin 15 | I/O β User I/O pin (Bank 1) |
| Pin 16 | TDI β JTAG Test Data In |
| Pin 17 | TMS β JTAG Test Mode Select |
| Pin 18 | TCK β JTAG Test Clock |
| Pin 19 | TDO β JTAG Test Data Out |
| Pin 20 | GND β Ground |
| Pin 21 | VCCINT β Core supply voltage (3.3 V) |
| Pin 22 | I/O β User I/O pin (Bank 1) |
| Pin 23 | I/O β User I/O pin (Bank 1) |
| Pin 24 | I/O β User I/O pin (Bank 2) |
| Pin 25 | I/O β User I/O pin (Bank 2) |
| Pin 26 | I/O β User I/O pin (Bank 2) |
| Pin 27 | I/O β User I/O pin (Bank 2) |
| Pin 28 | I/O β User I/O pin (Bank 2) |
| Pin 29 | I/O β User I/O pin (Bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (Bank 2) |
| Pin 32 | I/O β User I/O pin (Bank 2) |
| Pin 33 | I/O β User I/O pin (Bank 2) |
| Pin 34 | I/O β User I/O pin (Bank 2) |
| Pin 35 | I/O β User I/O pin (Bank 2) |
| Pin 36 | I/O β User I/O pin (Bank 2) |
| Pin 37 | I/O β User I/O pin (Bank 2) |
| Pin 38 | I/O β User I/O pin (Bank 2) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin (Bank 2) |
| Pin 41 | I/O β User I/O pin (Bank 2) |
| Pin 42 | I/O β User I/O pin (Bank 2) |
| Pin 43 | I/O β User I/O pin (Bank 3) |
| Pin 44 | I/O β User I/O pin (Bank 3) |
| Pin 45 | I/O β User I/O pin (Bank 3) |
| Pin 46 | I/O β User I/O pin (Bank 3) |
| Pin 47 | I/O β User I/O pin (Bank 3) |
| Pin 48 | I/O β User I/O pin (Bank 3) |
| Pin 49 | I/O β User I/O pin (Bank 3) |
| Pin 50 | GND β Ground |
| Pin 51 | INPUT/GCLK1 β Global Clock 1 input |
| Pin 52 | INPUT/GCLK3 β Global Clock 3 input |
| Pin 53 | INPUT/OE1 β Global OE 1 input |
| Pin 54 | INPUT/GCLRn β Global Clear input |
| Pin 55 | INPUT/OE2/GCLK2 β Global OE 2 / Global Clock 2 input |
| Pin 56 | INPUT/GCLK4 β Global Clock 4 input |
| Pin 57 | I/O β User I/O pin (Bank 3) |
| Pin 58 | I/O β User I/O pin (Bank 3) |
| Pin 59 | I/O β User I/O pin (Bank 3) |
| Pin 60 | VCCIO1 β Bank 1 I/O supply (2.5/3.3/5 V) |
| Pin 61 | I/O β User I/O pin (Bank 3) |
| Pin 62 | I/O β User I/O pin (Bank 3) |
| Pin 63 | I/O β User I/O pin (Bank 3) |
| Pin 64 | I/O β User I/O pin (Bank 3) |
| Pin 65 | I/O β User I/O pin (Bank 3) |
| Pin 66 | I/O β User I/O pin (Bank 3) |
| Pin 67 | I/O β User I/O pin (Bank 3) |
| Pin 68 | I/O β User I/O pin (Bank 3) |
| Pin 69 | I/O β User I/O pin (Bank 3) |
| Pin 70 | I/O β User I/O pin (Bank 3) |
| Pin 71 | I/O β User I/O pin (Bank 3) |
| Pin 72 | I/O β User I/O pin (Bank 3) |
| Pin 73 | I/O β User I/O pin (Bank 4) |
| Pin 74 | I/O β User I/O pin (Bank 4) |
| Pin 75 | GND β Ground |
| Pin 76 | VCCIO2 β Bank 2 I/O supply (2.5/3.3/5 V) |
| Pin 77 | I/O β User I/O pin (Bank 4) |
| Pin 78 | I/O β User I/O pin (Bank 4) |
| Pin 79 | I/O β User I/O pin (Bank 4) |
| Pin 80 | I/O β User I/O pin (Bank 4) |
| Pin 81 | I/O β User I/O pin (Bank 4) |
| Pin 82 | I/O β User I/O pin (Bank 4) |
| Pin 83 | I/O β User I/O pin (Bank 4) |
| Pin 84 | I/O β User I/O pin (Bank 4) |
| Pin 85 | I/O β User I/O pin (Bank 4) |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O pin (Bank 4) |
| Pin 88 | I/O β User I/O pin (Bank 4) |
| Pin 89 | I/O β User I/O pin (Bank 4) |
| Pin 90 | I/O β User I/O pin (Bank 4) |
| Pin 91 | I/O β User I/O pin (Bank 4) |
| Pin 92 | I/O β User I/O pin (Bank 1) |
| Pin 93 | I/O β User I/O pin (Bank 1) |
| Pin 94 | I/O β User I/O pin (Bank 1) |
| Pin 95 | VCCIO3 β Bank 3 I/O supply (2.5/3.3/5 V) |
| Pin 96 | I/O β User I/O pin (Bank 1) |
| Pin 97 | I/O β User I/O pin (Bank 1) |
| Pin 98 | I/O β User I/O pin (Bank 1) |
| Pin 99 | I/O β User I/O pin (Bank 1) |
| Pin 100 | I/O β User I/O pin (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETI100-7 is suitable for 6 applications: Industrial Bus Interface / Glue Logic, Address Decoding and Chip-Select Generation, State-Machine Controller for Power Sequencing, Legacy Peripheral Emulation and Bus Translation, LED Display Multiplexing and Panel Controllers, Telecom Line-Card Glue Logic.
Industrial Bus Interface / Glue Logic
The EPM7128AETI100-7's 128 macrocells and 84 user I/Os make it well-suited for bridging between microcontrollers, ASICs, and peripheral buses in industrial controllers. Its 7.5 ns pin-to-pin delay (tPD) keeps address decoding and chip-select generation deterministic, which is critical when the CPLD sits between an 80 MHz 32-bit MCU and asynchronous SRAM or peripheral FIFOs. MultiVolt I/O allows direct 5 V-3.3 V level shifting within the same device, eliminating external translator ICs. Designers commonly instantiate the EPM7128AETI100-7 in PLC backplanes, motor-control boards, and industrial sensor hubs where deterministic timing and legacy 5 V bus compatibility are required simultaneously.
Recommended
Address Decoding and Chip-Select Generation
The EPM7128AETI100-7's deterministic 7.5 ns tPD and 128 macrocells provide ample capacity to decode wide address buses (24-32 bits) and generate multiple chip-select strobes for memory banks, peripherals, and external ASICs. Because CPLD propagation delay is independent of routing complexity, a deeply nested decode tree still completes within the -7 timing budget. The MultiVolt I/O interface lets the CPLD directly drive 5 V SRAM chips while running its core at 3.3 V, removing the level-shifters that would otherwise sit in the CS path. Industrial embedded boards and telecom line cards historically relied on this part for memory-map decoding before FPGAs displaced CPLDs in greenfield designs.
Recommended
State-Machine Controller for Power Sequencing
Power-supply sequencers benefit from the EPM7128AETI100-7's non-volatile EEPROM configuration: the state machine boots instantly at POR with no FPGA-style configuration delay, enabling strict rail-to-rail sequencing in multi-rail systems. Designers build multi-state FSMs across the 8 LABs to sequence 3.3 V core, 1.8 V DDR, 1.0 V FPGA, and 5 V analog rails with programmable delays. The four dedicated global clock/clear/preset inputs double as hardware watchdog timers and power-good triggers. The industrial -40 C to +85 C temperature range makes this part acceptable for telecom shelf-power controllers and factory-floor PLC power sub-systems.
Recommended
Legacy Peripheral Emulation and Bus Translation
The EPM7128AETI100-7 is widely used to emulate older ISA-bus peripherals, SCSI controllers, or VME-bus interfaces on modern motherboards where the original logic chips have been discontinued. Its 128 macrocells can model decades-old glue-logic ASICs while presenting JTAG for board-test access. The JTAG IEEE 1149.1 boundary-scan interface also doubles as a board-level test access port (TAP), invaluable in production test for legacy aerospace, defense, and industrial-control boards where traceability is mandatory. Migration programs that need to extend the lifecycle of 1990s industrial PCs and telecom switches still source this part for board-repair and low-volume rebuilds.
Recommended
LED Display Multiplexing and Panel Controllers
Large LED-matrix displays and dot-matrix panels require high-frequency row-scanning and column-refresh logic that benefits from the EPM7128AETI100-7's 129.9 MHz counter frequency and 84 I/Os. Each LAB can drive a column decoder while the global clocks drive the row scanner, producing flicker-free refresh at 1 kHz or higher without burdening the host MCU. The MultiVolt I/O supports direct LED-driver interfaces (e.g., 5 V TPIC6B595 shift registers) alongside 3.3 V microcontrollers. Stadium scoreboards, traffic signs, and factory-floor HMI panels from the early 2000s frequently used this part for its deterministic refresh timing and instant-on non-volatile boot.
Recommended
Telecom Line-Card Glue Logic
Telecom line cards aggregate TDM, HDLC, and ATM traffic onto backplane buses, requiring deterministic timing, bus-arbitration logic, and multi-voltage I/O - exactly the EPM7128AETI100-7's design center. The MAX 7000A architecture's instant-on EEPROM boot makes this part ideal for hot-swap line-card designs where configuration must complete within a 100 ms insertion window. MultiVolt I/O handles the mix of 5 V and 3.3 V bus interfaces on legacy line cards. The industrial -40 C to +85 C range tolerates the airflow-restricted, elevated-temperature environments of central-office equipment cabinets. Long-lifecycle telecom integrators still maintain stock for repair purposes even though the part is officially obsolete.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETI100-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETI100-7N | EPM7128AETC100-7 | EPM7128AETC100-7N | EPM7128AETC100-10N | EPM7128AET1100-7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns | 10 ns (-33%) | 7.5 ns |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Lead-Free / RoHS | No (SnPb finish) | Yes (Pb-free finish) | No (SnPb finish) | Yes (Pb-free finish) | Yes (Pb-free finish) | [DATA_NEEDED] |
| Maximum Counter Frequency | 129.9 MHz | 129.9 MHz | 129.9 MHz | 129.9 MHz | 100 MHz (lower grade) | 129.9 MHz |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 |
| User I/Os | 84 | 84 | 84 | 84 | 84 | 84 |
Key Differentiators
- Industrial temperature range with 7.5 ns tPD (vs EPM7128AETC100-7)
- Faster speed grade (vs EPM7128AETC100-10N)
- MultiVolt I/O supports mixed-voltage systems (vs EPM7128AETI100-10)
Design Notes
Provide separate, well-decoupled supplies for VCCINT (3.3 V core) and each VCCIO bank (2.5 V, 3.3 V, or 5 V). Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCCINT and VCCIO pin pair, supplemented by a single 10 uF bulk capacitor per supply rail. Power sequencing is not required because the EEPROM configuration boots instantaneously at POR, but ramp rates should remain within the datasheet's 50 V/ms limit.
Route JTAG signals TMS, TCK, TDI, and TDO as a matched-length group with 4.7 kohm pull-ups on TMS and TDI to VCCIO1. Keep the JTAG chain out of the path of fast-edge signals from clock-output I/Os to avoid noise coupling into the TAP. Use the dedicated GCLK1-GCLK4 inputs for high-frequency clocks rather than routing clocks through general-purpose I/Os to preserve signal integrity.
Do not mix 5 V and 3.3 V I/O banks that share the same JTAG chain without buffering - level mismatch can damage the JTAG drivers. Always use the Quartus II Programmer (or compatible third-party programmer such as the BPM Microsystems) to program the EEPROM; in-circuit ISP works only if VCCINT is stable and JTAG pull-ups are present. Confirm that the -7 speed grade meets your timing budget before substituting a -10 grade; the slower part may violate set-up/hold requirements in high-frequency designs.
The EPM7128AETI100-7 in TQFP-100 typically dissipates under 1 W at full I/O toggle activity across all 84 outputs. The exposed thermal pad is not present on the TQFP-100 package, so board-level thermal relief comes from copper pours on the top and inner layers. For designs with continuous high-frequency I/O switching (e.g., 50 MHz+), ensure at least 1 square inch of ground copper is connected to GND pins 11, 20, 30, 39, 50, 75, and 86 to keep junction temperature below 125 C at the 85 C ambient upper bound.
Compliance Information
EPM7128AETI100-7 (non-N suffix) uses tin-lead finish and is not RoHS compliant. The -7N variant is the lead-free RoHS-compliant version. Industrial temperature grade is -40C to +85C. AEC-Q100 not applicable as CPLDs are not automotive-qualified. REACH and conflict-mineral declarations not stated in the public datasheet.
