EPM7128AETI100-7N vs EPM7128ATC100-10 Comparison
Detailed side-by-side comparison of EPM7128AETI100-7N by Altera and EPM7128ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteAltera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteSpecification Comparison
| Parameter | EPM7128AETI100-7N | EPM7128ATC100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 7000A | — |
| Family | MAX 7000A CPLD | MAX 7000A |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | — |
| Package | 100-pin TQFP (14x14 mm) | 100-pin TQFP (TC100) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (IEEE 1149.1 JTAG) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 2.5K |
| User I/O Pins | — | 68 |
| Pin-to-Pin Logic Delay | — | 4.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Speed Grade | — | -10 (10 ns) |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | — | EEPROM (non-volatile) |