EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
MPN: EPM7128AETI100-7N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $43.77 | $43.77 |
| 10 | $40.2 | $402.00 |
| 100 | $36.5 | $3,650.00 |
| 500 | $32 | $16,000.00 |
| 1,000 | $28.5 | $28,500.00 |
Drop-in alternatives for EPM7128AETI100-7N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7128AETI100-7N Maximum Ratings & Electrical Characteristics
| Series | MAX 7000A |
| Family | MAX 7000A CPLD |
| Macro Cells | 128 |
| Number of Usable Gates | 2,500 |
| Number of I/O | 84 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD max) | 7 ns |
| Maximum Operating Frequency (fCNT) | 129.9 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Process Technology | CMOS EEPROM |
| Package | 100-pin TQFP (14x14 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| RoHS Status | Compliant |
EPM7128AETI100-7N Pin Configuration
| Pin 1 | I/O β User I/O (Bank 1) |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | I/O β User I/O (Bank 1) |
| Pin 7 | I/O β User I/O (Bank 1) |
| Pin 8 | I/O β User I/O (Bank 1) |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | I/O β User I/O (Bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O (Bank 1) |
| Pin 13 | I/O β User I/O (Bank 1) |
| Pin 14 | I/O β User I/O (Bank 1) |
| Pin 15 | I/O β User I/O (Bank 1) |
| Pin 16 | I/O β User I/O (Bank 1) |
| Pin 17 | I/O β User I/O (Bank 1) |
| Pin 18 | I/O β User I/O (Bank 1) |
| Pin 19 | I/O β User I/O (Bank 1) |
| Pin 20 | I/O β User I/O (Bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (Bank 2) |
| Pin 23 | I/O β User I/O (Bank 2) |
| Pin 24 | I/O β User I/O (Bank 2) |
| Pin 25 | I/O β User I/O (Bank 2) |
| Pin 26 | I/O β User I/O (Bank 2) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | I/O β User I/O (Bank 2) |
| Pin 30 | I/O β User I/O (Bank 2) |
| Pin 31 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 32 | I/O β User I/O (Bank 2) |
| Pin 33 | I/O β User I/O (Bank 2) |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | I/O β User I/O (Bank 2) |
| Pin 37 | I/O β User I/O (Bank 2) |
| Pin 38 | I/O β User I/O (Bank 2) |
| Pin 39 | I/O β User I/O (Bank 2) |
| Pin 40 | I/O β User I/O (Bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O (Bank 2) |
| Pin 43 | I/O β User I/O (Bank 2) |
| Pin 44 | I/O β User I/O (Bank 2) |
| Pin 45 | I/O β User I/O (Bank 2) |
| Pin 46 | I/O β User I/O (Bank 2) |
| Pin 47 | I/O β User I/O (Bank 2) |
| Pin 48 | I/O β User I/O (Bank 2) |
| Pin 49 | I/O β User I/O (Bank 2) |
| Pin 50 | I/O β User I/O (Bank 2) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O (Bank 3) |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | I/O β User I/O (Bank 3) |
| Pin 55 | I/O β User I/O (Bank 3) |
| Pin 56 | I/O β User I/O (Bank 3) |
| Pin 57 | I/O β User I/O (Bank 3) |
| Pin 58 | I/O β User I/O (Bank 3) |
| Pin 59 | I/O β User I/O (Bank 3) |
| Pin 60 | I/O β User I/O (Bank 3) |
| Pin 61 | I/O β User I/O (Bank 3) |
| Pin 62 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 63 | I/O β User I/O (Bank 3) |
| Pin 64 | I/O β User I/O (Bank 3) |
| Pin 65 | I/O β User I/O (Bank 3) |
| Pin 66 | I/O β User I/O (Bank 3) |
| Pin 67 | I/O β User I/O (Bank 3) |
| Pin 68 | I/O β User I/O (Bank 3) |
| Pin 69 | I/O β User I/O (Bank 3) |
| Pin 70 | I/O β User I/O (Bank 3) |
| Pin 71 | I/O β User I/O (Bank 3) |
| Pin 72 | I/O β User I/O (Bank 3) |
| Pin 73 | GND β Ground |
| Pin 74 | I/O β User I/O (Bank 3) |
| Pin 75 | I/O β User I/O (Bank 3) |
| Pin 76 | I/O β User I/O (Bank 3) |
| Pin 77 | I/O β User I/O (Bank 3) |
| Pin 78 | I/O β User I/O (Bank 3) |
| Pin 79 | I/O β User I/O (Bank 3) |
| Pin 80 | I/O β User I/O (Bank 3) |
| Pin 81 | I/O β User I/O (Bank 3) |
| Pin 82 | I/O β User I/O (Bank 3) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O (Bank 4) |
| Pin 85 | I/O β User I/O (Bank 4) |
| Pin 86 | INPUT/GCLK β Global clock input (Bank 4) |
| Pin 87 | INPUT/OE1 β Global output enable 1 (Bank 4) |
| Pin 88 | INPUT/GCLRn β Global clear (Bank 4) |
| Pin 89 | INPUT/OE2 β Global output enable 2 (Bank 4) |
| Pin 90 | TDI β JTAG Test Data In |
| Pin 91 | TMS β JTAG Test Mode Select |
| Pin 92 | TCK β JTAG Test Clock |
| Pin 93 | VCCIO3 β I/O Bank 3 supply voltage |
| Pin 94 | VCCINT β Core supply voltage 3.3 V |
| Pin 95 | GND β Ground |
| Pin 96 | VCCIO4 β I/O Bank 4 supply voltage |
| Pin 97 | TDO β JTAG Test Data Out |
| Pin 98 | I/O β User I/O (Bank 4) |
| Pin 99 | I/O β User I/O (Bank 4) |
| Pin 100 | I/O β User I/O (Bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETI100-7N is suitable for 6 applications: Bus Interface Glue Logic, Address Decoding for Embedded Microprocessors, Industrial Automation State-Machine Controller, Telecom I/O Expansion and Level Translation, Legacy MAX 7000S Drop-In Upgrade Path, JTAG Boundary-Scan Test Controller.
Bus Interface Glue Logic
The EPM7128AETI100-7N's 84 user I/Os and deterministic 7 ns pin-to-pin tPD make it well-suited for PCI-to-ISA bridge logic, bus address decoding, and wait-state generation in legacy embedded systems. Its 3.3 V VCCINT with multi-volt I/O (2.5 V / 3.3 V / 5.0 V) lets it interface both 5.0 V legacy microcontrollers and 3.3 V modern processors on the same board without external level shifters. Compared to discrete 74-series glue logic, a single CPLD replaces dozens of packages while the JTAG ISP allows post-assembly bug fixes. The 129.9 MHz fCNT supports high-bandwidth bus cycles including PCI 33 MHz timing.
Recommended
Address Decoding for Embedded Microprocessors
With 128 macrocells the EPM7128AETI100-7N can implement complex address-decoder state machines for 32-bit embedded microprocessors (e.g., PowerPC, ARM7/9, MIPS) where multiple chip-select lines must be generated from a unified memory map. Each macrocell functions as a product-term-based decoder with built-in registers, providing glitch-free chip-select outputs that are immune to logic-utility-induced delays - a key advantage over FPGA-based decoders. The industrial -40C to +85C range suits factory and outdoor telecom embedded systems.
Recommended
Industrial Automation State-Machine Controller
The EPM7128AETI100-7N's non-volatile EEPROM configuration ensures instant-on state-machine operation at power-up without external boot memory, critical for industrial PLC and motor-control systems where determinism and fast startup are required. The 84 I/Os can directly drive opto-isolated inputs and 24 V relay/solenoid outputs via external drivers. Industrial temperature grade (-40C to +85C) and multi-volt I/O tolerance allow direct interfacing to legacy 5.0 V industrial sensor busses while the 3.3 V core keeps power dissipation modest in enclosed cabinets.
Recommended
Telecom I/O Expansion and Level Translation
The EPM7128AETI100-7N's multi-volt I/O bank (VCCIO selectable per bank) makes it a flexible level translator between 5.0 V TDM/PCM telecom busses and 3.3 V processor peripherals in central-office and base-station equipment. Each I/O pin can be independently configured as input, output, or bidirectional, supporting complex protocol bridging. The 100-pin TQFP footprint with 84 I/Os gives ample headroom for 16-port E1/T1 fan-out, and JTAG ISP allows remote firmware updates via boundary-scan tools.
Recommended
Legacy MAX 7000S Drop-In Upgrade Path
The EPM7128AETI100-7N is pin-compatible with the legacy 5.0 V MAX 7000S family (EPM7128SQC100, EPM7128STC100), allowing direct PCB-reuse migration to a 3.3 V core while preserving the original 5.0 V I/O behavior via the multi-volt VCCIO. Engineers can redesign the power tree to 3.3 V while reusing the same PCB footprint and JTAG programming infrastructure (Quartus Prime). This makes the EPM7128AETI100-7N ideal for cost-down refreshes of legacy telecom and industrial designs.
Recommended
JTAG Boundary-Scan Test Controller
The EPM7128AETI100-7N's IEEE 1149.1 JTAG interface supports both in-system programming and boundary-scan test (BST) of the surrounding PCB cluster, eliminating the need for a dedicated test access port controller. With 84 user I/Os the CPLD can serve as a cluster-test hub for boards containing multiple JTAG devices, daisy-chaining TAP signals. The non-volatile EEPROM configuration means the BST infrastructure is available immediately at power-up without FPGA-style configuration delay, simplifying production test flows.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETI100-7N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETI100-7 | EPM7128AETC100-7N | EPM7128AETC100-10N |
|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Macro Cells | 128 | 128 | 128 | 128 |
| User I/O | 84 | 84 | 84 | 84 |
| Propagation Delay (tPD) | 7 ns | 7 ns | 7 ns | 10 ns |
| Max Frequency (fCNT) | 129.9 MHz | 129.9 MHz | 129.9 MHz | 100 MHz |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Unit Price (qty 1, as of 2026-09-13) | ~$43.77 | ~$40.00 | ~$32.00 | ~$28.00 |
Key Differentiators
- Industrial temperature grade with full pin compatibility (vs EPM7128AETC100-7N)
- 7 ns tPD speed grade with same pinout as 10 ns variant (vs EPM7128AETC100-10N)
- Multi-volt I/O for direct 5.0 V/3.3 V mixing (vs EPM7128SQC100 (legacy 5.0 V MAX 7000S))
Design Notes
The EPM7128AETI100-7N requires separate VCCINT (3.0 V to 3.6 V, core) and VCCIO (2.5 V / 3.3 V / 5.0 V, I/O banks) supplies. Each VCCIO pin must be decoupled with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 uF tantalum per bank. Per the MAX 7000A datasheet, all GND pins must be connected to a common ground plane - floating GND pins cause I/O behavior errors during ISP programming.
Route the four JTAG pins (TCK, TMS, TDI, TDO) as a matched-length chain with no stubs to avoid signal integrity issues during in-system programming. The global clock (INPUT/GCLK, pin 86) and global clear (INPUT/GCLRn, pin 88) traces should be kept short and shielded with ground pour on both sides. Per Altera application note AN-95, the TCK signal should be buffered if driving more than three devices on a JTAG chain.
Do not leave any VCCIO pin floating - unused I/O banks still require VCCIO supply connection. The multi-volt I/O feature requires that each I/O bank's VCCIO be set BEFORE any I/O pin is driven; floating VCCIO can cause latch-up. The 'N' suffix indicates lead-free / RoHS-compliant packaging - older non-N variants may contain lead solder and fail RoHS inspection. Verify JTAG chain integrity by reading the device IDCODE before programming.
Compliance Information
'N' suffix per Altera/Intel part-number convention indicates lead-free, RoHS-compliant terminal finish. Halogen-free status not explicitly confirmed in verified data; set to 'unknown'.
