EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
MPN: EPM7128ATC100-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.45 | $9.45 |
| 10 | $8.2 | $82.00 |
| 100 | $6.95 | $695.00 |
| 500 | $5.85 | $2,925.00 |
| 1,000 | $4.95 | $4,950.00 |
Drop-in alternatives for EPM7128ATC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC100-10
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPM7128AETC100-10N
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128AETI100-7
β Drop-Inβ In Stock
$30.1 / Unit
View Datasheet βEPM7128AETI100-7N
β Drop-Inβ In Stock
$28.5 / Unit
View Datasheet βEPM7128AET1100-7
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEPM7128STC100-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ATC100-10 Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000A |
| Architecture | Multiple Array MatriX (MAX) |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 4 |
| Usable Gates | 2.5K |
| User I/O Pins | 68 |
| Pin-to-Pin Logic Delay | 4.5 ns |
| Counter Frequency (max) | 227.3 MHz |
| Speed Grade | -10 (10 ns) |
| Core Supply Voltage | 3.3 V |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Package | 100-pin TQFP (TC100) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
EPM7128ATC100-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell) |
| Pin 2 | I/O β User I/O pin (macrocell) |
| Pin 3 | I/O β User I/O pin (macrocell) |
| Pin 4 | I/O β User I/O pin (macrocell) |
| Pin 5 | I/O β User I/O pin (macrocell) |
| Pin 6 | I/O β User I/O pin (macrocell) |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β User I/O pin (macrocell) |
| Pin 9 | I/O β User I/O pin (macrocell) |
| Pin 10 | I/O β User I/O pin (macrocell) |
| Pin 11 | I/O β User I/O pin (macrocell) |
| Pin 12 | I/O β User I/O pin (macrocell) |
| Pin 13 | I/O β User I/O pin (macrocell) |
| Pin 14 | I/O β User I/O pin (macrocell) |
| Pin 15 | I/O β User I/O pin (macrocell) |
| Pin 16 | I/O β User I/O pin (macrocell) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin (macrocell) |
| Pin 19 | I/O β User I/O pin (macrocell) |
| Pin 20 | I/O β User I/O pin (macrocell) |
| Pin 21 | I/O β User I/O pin (macrocell) |
| Pin 22 | I/O β User I/O pin (macrocell) |
| Pin 23 | I/O β User I/O pin (macrocell) |
| Pin 24 | I/O β User I/O pin (macrocell) |
| Pin 25 | I/O β User I/O pin (macrocell) |
| Pin 26 | I/O β User I/O pin (macrocell) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin (macrocell) |
| Pin 29 | I/O β User I/O pin (macrocell) |
| Pin 30 | I/O β User I/O pin (macrocell) |
| Pin 31 | I/O β User I/O pin (macrocell) |
| Pin 32 | I/O β User I/O pin (macrocell) |
| Pin 33 | I/O β User I/O pin (macrocell) |
| Pin 34 | I/O β User I/O pin (macrocell) |
| Pin 35 | I/O β User I/O pin (macrocell) |
| Pin 36 | I/O β User I/O pin (macrocell) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (macrocell) |
| Pin 39 | I/O β User I/O pin (macrocell) |
| Pin 40 | I/O β User I/O pin (macrocell) |
| Pin 41 | I/O β User I/O pin (macrocell) |
| Pin 42 | I/O β User I/O pin (macrocell) |
| Pin 43 | I/O β User I/O pin (macrocell) |
| Pin 44 | I/O β User I/O pin (macrocell) |
| Pin 45 | I/O β User I/O pin (macrocell) |
| Pin 46 | I/O β User I/O pin (macrocell) |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O pin (macrocell) |
| Pin 49 | I/O β User I/O pin (macrocell) |
| Pin 50 | I/O β User I/O pin (macrocell) |
| Pin 51 | I/O β User I/O pin (macrocell) |
| Pin 52 | I/O β User I/O pin (macrocell) |
| Pin 53 | I/O β User I/O pin (macrocell) |
| Pin 54 | I/O β User I/O pin (macrocell) |
| Pin 55 | I/O β User I/O pin (macrocell) |
| Pin 56 | I/O β User I/O pin (macrocell) |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O pin (macrocell) |
| Pin 59 | I/O β User I/O pin (macrocell) |
| Pin 60 | I/O β User I/O pin (macrocell) |
| Pin 61 | I/O β User I/O pin (macrocell) |
| Pin 62 | I/O β User I/O pin (macrocell) |
| Pin 63 | I/O β User I/O pin (macrocell) |
| Pin 64 | I/O β User I/O pin (macrocell) |
| Pin 65 | I/O β User I/O pin (macrocell) |
| Pin 66 | I/O β User I/O pin (macrocell) |
| Pin 67 | GND β Ground |
| Pin 68 | I/O β User I/O pin (macrocell) |
| Pin 69 | I/O β User I/O pin (macrocell) |
| Pin 70 | I/O β User I/O pin (macrocell) |
| Pin 71 | TDI β JTAG Test Data In |
| Pin 72 | TMS β JTAG Test Mode Select |
| Pin 73 | TCK β JTAG Test Clock |
| Pin 74 | VCC β 3.3V core supply |
| Pin 75 | GND β Ground |
| Pin 76 | TDO β JTAG Test Data Out |
| Pin 77 | I/O β User I/O pin (macrocell) |
| Pin 78 | I/O β User I/O pin (macrocell) |
| Pin 79 | I/O β User I/O pin (macrocell) |
| Pin 80 | I/O β User I/O pin (macrocell) |
| Pin 81 | I/O β User I/O pin (macrocell) |
| Pin 82 | I/O β User I/O pin (macrocell) |
| Pin 83 | I/O β User I/O pin (macrocell) |
| Pin 84 | I/O β User I/O pin (macrocell) |
| Pin 85 | GND β Ground |
| Pin 86 | I/O β User I/O pin (macrocell) |
| Pin 87 | I/O β User I/O pin (macrocell) |
| Pin 88 | I/O β User I/O pin (macrocell) |
| Pin 89 | I/O β User I/O pin (macrocell) |
| Pin 90 | I/O β User I/O pin (macrocell) |
| Pin 91 | I/O β User I/O pin (macrocell) |
| Pin 92 | I/O β User I/O pin (macrocell) |
| Pin 93 | I/O β User I/O pin (macrocell) |
| Pin 94 | I/O β User I/O pin (macrocell) |
| Pin 95 | GND β Ground |
| Pin 96 | I/O β User I/O pin (macrocell) |
| Pin 97 | I/O β User I/O pin (macrocell) |
| Pin 98 | I/O β User I/O pin (macrocell) |
| Pin 99 | I/O β User I/O pin (macrocell) |
| Pin 100 | I/O β User I/O pin (macrocell) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ATC100-10 is suitable for 6 applications: PCI Bus Interface Glue Logic, Microprocessor Address Decoding, Legacy 5V-to-3.3V Level Shifting, State Machine and Sequencer Controllers, Peripheral Bus Adapters (ISA, VME, PC/104), Embedded Computing Glueless Peripherals.
PCI Bus Interface Glue Logic
The EPM7128ATC100-10's 4.5 ns pin-to-pin logic delay and 33 MHz PCI bus compatibility make it well suited for implementing PCI target interface glue logic, address decode, and command/byte-enable generation. With 128 macrocells it can host a complete 32-bit PCI target state machine plus several custom registers. Placed between the PCI bus connector and a downstream ASIC, the device consumes negligible power (under 300 mW typical at 3.3V) and provides deterministic timing critical for PCI bus cycles. Compared to discrete 74-series logic, the CPLD integration reduces PCB area by 5-10x while preserving the 10 ns worst-case latency budget.
Recommended
Microprocessor Address Decoding
The 128 macrocells of the EPM7128ATC100-10 are ideal for complex memory and peripheral address-decoding tasks in 16-bit and 32-bit microprocessor systems. Each macrocell implements a sum-of-products term that maps one or more address lines plus chip-select qualifiers to a single decode output. With 68 user I/O pins, the device can decode multiple banks of memory, peripherals, and I/O devices simultaneously while leaving dedicated JTAG pins for in-system reprogramming. The 4.5 ns propagation delay ensures zero-wait-state operation for processors up to 50 MHz bus frequency, and the MultiVolt I/O interface allows direct 5V-to-3.3V interfacing with legacy MCUs.
Recommended
Legacy 5V-to-3.3V Level Shifting
The EPM7128ATC100-10's MultiVolt I/O interface supports 5.0V, 3.3V, and 2.5V logic levels simultaneously, allowing it to act as a bidirectional level shifter between legacy 5V peripherals and modern 3.3V ASICs or processors. Each I/O bank can be configured independently, enabling mixed-voltage designs on a single chip. Typical use cases include interfacing 5V sensors or industrial buses to 3.3V microcontrollers without external level-translator ICs, reducing BOM cost and PCB area. The 3.3V core consumes approximately 50% less power than equivalent 5V-only CPLDs while preserving full 5V tolerance on the I/O pins.
Recommended
State Machine and Sequencer Controllers
CPLDs excel at implementing deterministic finite state machines, and the EPM7128ATC100-10's 128 macrocells support FSMs of substantial complexity including multiple parallel state machines with shared inputs. Per the manufacturer datasheet, each macrocell includes a flip-flop for registered outputs, enabling fully synchronous state-machine designs with predictable timing. Industrial sequencer applications (machine tool controllers, conveyor logic, test equipment) benefit from the 10 ns pin-to-pin delay for fast event response. The non-volatile EEPROM configuration means the sequencer state at power-on is deterministic, eliminating the boot-time variability of SRAM-based FPGAs.
Recommended
Peripheral Bus Adapters (ISA, VME, PC/104)
Legacy peripheral bus standards (ISA, VME, PC/104) still see widespread use in industrial and embedded computing, where the EPM7128ATC100-10 serves as a compact bus bridge and adapter. The device can implement custom address mapping, interrupt steering, and DMA handshaking for adding modern peripherals to legacy bus systems. The 100-pin TQFP package provides 68 user I/O pins, sufficient for full 16-bit data plus 24-bit address plus control signals. Quartus II software supports the part for design entry, simulation, and JTAG programming using USB-Blaster or ByteBlaster cables.
Recommended
Embedded Computing Glueless Peripherals
The EPM7128ATC100-10 enables microprocessors and microcontrollers to interface with peripherals that lack a native bus interface, implementing custom protocols, FIFO buffers, and timing generators. With 128 macrocells and 68 I/O pins, designers can implement multiple peripherals (custom UARTs, SPI controllers, PWM generators, capture timers) on a single CPLD, reducing system cost and board area. The 4.5 ns propagation delay supports real-time protocol timing for high-speed serial interfaces. EEPROM-backed configuration means peripherals come up instantly at power-on, critical for boot-loader and system-controller roles.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ATC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC100-10 | EPM7128AETC100-10N | EPM7128AETI100-7 | EPM7128AETI100-7N | EPM7128AET1100-7 | EPM7128STC100-15 |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Speed Grade | -10 (10 ns) | -10 (10 ns) | -10 (10 ns) | -7 (faster) | -7 (faster) | -7 (faster) | -15 (slower) |
| Pin-to-Pin Delay | 4.5 ns | 4.5 ns | 4.5 ns | 5 ns (industrial) | 5 ns (industrial) | 5 ns (industrial) | 15 ns |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 5.0 V |
| Lifecycle Status | Obsolete | Active | Active | Active | Active | Active | Obsolete |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000S |
Key Differentiators
- MultiVolt I/O interface for mixed-voltage designs (vs MAX 7000S EPM7128STC100-15)
- 4.5 ns pin-to-pin delay with 227.3 MHz internal frequency (vs EPM7064AETC100-10)
- Standard 10 ns speed grade for legacy designs (vs EPM7128AETC100-7 (7 ns speed grade))
Design Notes
The EPM7128ATC100-10 requires a clean 3.3V core supply with at least 100 mA of headroom for ISP programming current spikes. Place a 100 uF bulk capacitor and a 0.1 uF decoupling capacitor within 1 cm of each VCC pin (TQFP-100 has multiple VCC pins distributed along all four sides). For mixed-voltage designs, route 5V tolerant I/O banks separately from 3.3V-only banks to prevent back-powering through I/O pins.
Route the JTAG signals (TCK, TMS, TDI, TDO) as a controlled-impedance group with series 33 ohm damping resistors near the CPLD. Keep JTAG traces away from switching signals and add a ground guard on both sides. For in-system programming via USB-Blaster or ByteBlaster, expose a 2x5 0.1 inch JTAG header on the PCB with VCC sense pin connected to the CPLD's 3.3V rail for buffer reference.
Do not leave unused I/O pins floating; configure them as outputs driving logic-low in the Quartus project to minimize in-rush current at power-up. Avoid using GCLK (global clock) pins for non-clock signals, as this prevents the macrocell from using the fast global clock network. When migrating from the 5V MAX 7000S to the 3.3V MAX 7000A, verify I/O voltage compatibility - the MAX 7000A core is 3.3V-only even though its I/O pins are 5V tolerant.
Compliance Information
RoHS and lead-free status not confirmed in verified web data - consult Rochester Electronics documentation or original Altera datasheet. The -10N suffix variants (EPM7128AETC100-10N) are typically lead-free/RoHS-compliant per Altera/Intel naming convention. AEC-Q100 is not applicable as this is a logic device, not an automotive-qualified part.
