EPM7128ATI100-10 vs EPM7128AETI100-7N Comparison
Detailed side-by-side comparison of EPM7128ATI100-10 by Altera and EPM7128AETI100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ Last Time BuyAltera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteSpecification Comparison
| Parameter | EPM7128ATI100-10 | EPM7128AETI100-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Series | MAX 7000A | MAX 7000A |
| Family | MAX 7000A (MAX II of MAX 7000 series) | MAX 7000A CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks (LABs) | 4 | 8 |
| Usable Gates | 2,500 | — |
| Number of I/O Pins | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V |
| I/O Standard | MultiVolt (2.5V / 3.3V / 5.0V tolerant) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Operating Temperature | -40C to +85C (Industrial, 'I' suffix) | -40C to +85C (Industrial) |
| Package | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14x14 mm) |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| RoHS Status | Non-compliant (legacy part) | Compliant |
| Mounting Type | Surface Mount | Surface Mount |
| Macro Cells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |