EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
MPN: EPM7128ATI100-10 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $22.26 | $22.26 |
| 10 | $20.95 | $209.50 |
| 100 | $18.19 | $1,819.00 |
| 500 | $15.5 | $7,750.00 |
| 1,000 | $13.85 | $13,850.00 |
Drop-in alternatives for EPM7128ATI100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC100-10
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPM7128AETC100-10N
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$9.95 / Unit
View Datasheet βEPM7128AETI100-7
β Drop-Inβ In Stock
$30.1 / Unit
View Datasheet βEPM7128AETI100-7N
β Drop-Inβ In Stock
$28.5 / Unit
View Datasheet βEPM7128ATC100-7F
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128ATI100-10 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000A |
| Family | MAX 7000A (MAX II of MAX 7000 series) |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) |
| Number of Macrocells | 128 |
| Number of Logic Array Blocks (LABs) | 4 |
| Usable Gates | 2,500 |
| Number of I/O Pins | 68 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency (fMAX) | 87 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Standard | MultiVolt (2.5V / 3.3V / 5.0V tolerant) |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) |
| Operating Temperature | -40C to +85C (Industrial, 'I' suffix) |
| Package | 100-pin TQFP (14x14 mm) |
| Process Technology | CMOS EEPROM |
| RoHS Status | Non-compliant (legacy part) |
| Mounting Type | Surface Mount |
EPM7128ATI100-10 Pin Configuration
| Pin 1 | I/O β User I/O (macrocell I/O) |
| Pin 2 | I/O β User I/O (macrocell I/O) |
| Pin 3 | I/O β User I/O (macrocell I/O) |
| Pin 4 | I/O β User I/O (macrocell I/O) |
| Pin 5 | I/O β User I/O (macrocell I/O) |
| Pin 6 | I/O β User I/O (macrocell I/O) |
| Pin 7 | I/O β User I/O (macrocell I/O) |
| Pin 8 | I/O β User I/O (macrocell I/O) |
| Pin 9 | I/O β User I/O (macrocell I/O) |
| Pin 10 | I/O β User I/O (macrocell I/O) |
| Pin 11 | I/O β User I/O (macrocell I/O) |
| Pin 12 | I/O β User I/O (macrocell I/O) |
| Pin 13 | I/O β User I/O (macrocell I/O) |
| Pin 14 | I/O β User I/O (macrocell I/O) |
| Pin 15 | I/O β User I/O (macrocell I/O) |
| Pin 16 | I/O β User I/O (macrocell I/O) |
| Pin 17 | I/O β User I/O (macrocell I/O) |
| Pin 18 | I/O β User I/O (macrocell I/O) |
| Pin 19 | I/O β User I/O (macrocell I/O) |
| Pin 20 | I/O β User I/O (macrocell I/O) |
| Pin 21 | I/O β User I/O (macrocell I/O) |
| Pin 22 | I/O β User I/O (macrocell I/O) |
| Pin 23 | I/O β User I/O (macrocell I/O) |
| Pin 24 | I/O β User I/O (macrocell I/O) |
| Pin 25 | I/O β User I/O (macrocell I/O) |
| Pin 26 | I/O β User I/O (macrocell I/O) |
| Pin 27 | I/O β User I/O (macrocell I/O) |
| Pin 28 | I/O β User I/O (macrocell I/O) |
| Pin 29 | I/O β User I/O (macrocell I/O) |
| Pin 30 | I/O β User I/O (macrocell I/O) |
| Pin 31 | I/O β User I/O (macrocell I/O) |
| Pin 32 | I/O β User I/O (macrocell I/O) |
| Pin 33 | I/O β User I/O (macrocell I/O) |
| Pin 34 | I/O β User I/O (macrocell I/O) |
| Pin 35 | I/O β User I/O (macrocell I/O) |
| Pin 36 | I/O β User I/O (macrocell I/O) |
| Pin 37 | I/O β User I/O (macrocell I/O) |
| Pin 38 | I/O β User I/O (macrocell I/O) |
| Pin 39 | I/O β User I/O (macrocell I/O) |
| Pin 40 | I/O β User I/O (macrocell I/O) |
| Pin 41 | I/O β User I/O (macrocell I/O) |
| Pin 42 | I/O β User I/O (macrocell I/O) |
| Pin 43 | I/O β User I/O (macrocell I/O) |
| Pin 44 | I/O β User I/O (macrocell I/O) |
| Pin 45 | GCLK1 β Global clock input 1 |
| Pin 46 | GCLRn β Global clear input |
| Pin 47 | OE2 β Global output enable 2 (or user I/O) |
| Pin 48 | I/O β User I/O (macrocell I/O) |
| Pin 49 | I/O β User I/O (macrocell I/O) |
| Pin 50 | I/O β User I/O (macrocell I/O) |
| Pin 51 | I/O β User I/O (macrocell I/O) |
| Pin 52 | I/O β User I/O (macrocell I/O) |
| Pin 53 | I/O β User I/O (macrocell I/O) |
| Pin 54 | I/O β User I/O (macrocell I/O) |
| Pin 55 | I/O β User I/O (macrocell I/O) |
| Pin 56 | I/O β User I/O (macrocell I/O) |
| Pin 57 | I/O β User I/O (macrocell I/O) |
| Pin 58 | I/O β User I/O (macrocell I/O) |
| Pin 59 | I/O β User I/O (macrocell I/O) |
| Pin 60 | I/O β User I/O (macrocell I/O) |
| Pin 61 | I/O β User I/O (macrocell I/O) |
| Pin 62 | I/O β User I/O (macrocell I/O) |
| Pin 63 | I/O β User I/O (macrocell I/O) |
| Pin 64 | I/O β User I/O (macrocell I/O) |
| Pin 65 | I/O β User I/O (macrocell I/O) |
| Pin 66 | I/O β User I/O (macrocell I/O) |
| Pin 67 | I/O β User I/O (macrocell I/O) |
| Pin 68 | I/O β User I/O (macrocell I/O) |
| Pin 69 | I/O β User I/O (macrocell I/O) |
| Pin 70 | I/O β User I/O (macrocell I/O) |
| Pin 71 | I/O β User I/O (macrocell I/O) |
| Pin 72 | I/O β User I/O (macrocell I/O) |
| Pin 73 | I/O β User I/O (macrocell I/O) |
| Pin 74 | I/O β User I/O (macrocell I/O) |
| Pin 75 | TDI β JTAG Test Data In |
| Pin 76 | TMS β JTAG Test Mode Select |
| Pin 77 | TCK β JTAG Test Clock |
| Pin 78 | I/O β User I/O (macrocell I/O) |
| Pin 79 | I/O β User I/O (macrocell I/O) |
| Pin 80 | I/O β User I/O (macrocell I/O) |
| Pin 81 | I/O β User I/O (macrocell I/O) |
| Pin 82 | I/O β User I/O (macrocell I/O) |
| Pin 83 | I/O β User I/O (macrocell I/O) |
| Pin 84 | I/O β User I/O (macrocell I/O) |
| Pin 85 | I/O β User I/O (macrocell I/O) |
| Pin 86 | GCLK2 β Global clock input 2 |
| Pin 87 | OE1 β Global output enable 1 (or user I/O) |
| Pin 88 | I/O β User I/O (macrocell I/O) |
| Pin 89 | I/O β User I/O (macrocell I/O) |
| Pin 90 | I/O β User I/O (macrocell I/O) |
| Pin 91 | I/O β User I/O (macrocell I/O) |
| Pin 92 | I/O β User I/O (macrocell I/O) |
| Pin 93 | I/O β User I/O (macrocell I/O) |
| Pin 94 | I/O β User I/O (macrocell I/O) |
| Pin 95 | I/O β User I/O (macrocell I/O) |
| Pin 96 | I/O β User I/O (macrocell I/O) |
| Pin 97 | TDO β JTAG Test Data Out |
| Pin 98 | I/O β User I/O (macrocell I/O) |
| Pin 99 | I/O β User I/O (macrocell I/O) |
| Pin 100 | I/O β User I/O (macrocell I/O) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ATI100-10 is suitable for 6 applications: Microprocessor Bus Interface & Glue Logic, Address Decoding & Chip-Select Generation, State-Machine & Sequencer Controllers, Telecom Line-Card Glue & Network Peripherals, Industrial Control & Automation Logic, Legacy 5V-to-3.3V System Migration Bridge.
Microprocessor Bus Interface & Glue Logic
The EPM7128ATI100-10's 128 macrocells and 68 user I/O make it well-suited for bridging 8/16/32-bit microprocessors to peripherals with mismatched bus widths or voltage levels. With 10 ns pin-to-pin delay it easily meets the setup/hold timing of 40-66 MHz processor buses, and its MultiVolt I/O enables direct connection to 5V peripherals from a 3.3V CPLD supply. The deterministic timing of the MAX 7000A architecture eliminates the timing-closure iterations typical of FPGAs.
Recommended
Address Decoding & Chip-Select Generation
Address decoding for memory-mapped peripherals and chip-select generation in embedded systems is a canonical CPLD application that exploits the EPM7128ATI100-10's wide product-term logic and 10 ns propagation delay. Each macrocell supports up to 32 product terms, allowing complex address-match equations across 24-bit address spaces with single-clock latency. Industrial -40C to +85C operation makes the part suitable for factory-floor controllers and outdoor telecom equipment.
Recommended
State-Machine & Sequencer Controllers
State machines for protocol engines (UART, SPI, I2C controllers), motor-control sequencers, and test-equipment timing benefit from the EPM7128ATI100-10's deterministic 10 ns tPD and zero-power CMOS EEPROM configuration. 128 macrocells provide enough capacity for 16-32 state FSMs with extensive output decoding, and the 4 LAB architecture gives predictable placement and routing. Instant-on operation eliminates the boot-time delay common to SRAM-based FPGAs.
Recommended
Telecom Line-Card Glue & Network Peripherals
The EPM7128ATI100-10's MultiVolt I/O (2.5V/3.3V/5V tolerant) and industrial temperature grade suit telecom line cards for T1/E1, DSLAM, and legacy SONET/SDH equipment, where it performs bus-width adaptation, clock-domain crossing, and interrupt-aggregation glue. Its 100-pin TQFP footprint exposes 68 user I/O - sufficient for 8-bit TDM buses plus supervisory I/O. JTAG boundary-scan support enables in-system test (BST) for board-level manufacturing coverage.
Recommended
Industrial Control & Automation Logic
In PLCs, motor drives, and process-control I/O modules, the EPM7128ATI100-10 replaces discrete 74-series glue logic with a single integrated device, reducing PCB area by 60-70% and improving field reliability. Industrial -40C to +85C operation handles factory-floor thermal extremes, and the EEPROM-based configuration retains logic through power cycles without a boot PROM. 128 macrocells comfortably fit encoder/decoder logic, watchdog timers, and isolated-signal conditioning sequencers.
Recommended
Legacy 5V-to-3.3V System Migration Bridge
When migrating a legacy 5V MAX 7000 design to 3.3V, the EPM7128ATI100-10 provides a near-identical function with 2.5V/3.3V/5V-tolerant I/O that can interface directly to existing 5V peripherals on input pins, simplifying board rework. The 100-pin TQFP package pinout matches the 5V MAX 7000 family in the same footprint, allowing re-use of existing PCB layouts. Designers should verify all VCC pins are re-routed to 3.3V and that 5V-only output drive strengths are within receiver tolerances.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ATI100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC100-10 | EPM7128AETI100-7 | EPM7128AETI100-10N | EPM7128ATC100-7F |
|---|---|---|---|---|---|
| Package | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14x14 mm) - same | 100-pin TQFP (14x14 mm) - same | 100-pin TQFP (14x14 mm) - same | 100-pin TQFP (14x14 mm) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns (same speed grade) | 7 ns (faster grade) | 10 ns (same speed grade) | 7 ns (faster grade) |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| RoHS Status | Non-compliant (legacy) | Non-compliant (legacy) | Non-compliant (legacy) | Compliant (lead-free) | [DATA_NEEDED] |
| Logic Array Blocks | 4 | 4 | 4 | 4 | 4 |
| User I/O | 68 | 68 | 68 | 68 | 68 |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 |
| Supply Voltage | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V |
Key Differentiators
- Industrial -40C to +85C temperature grade (vs EPM7128AETC100-10)
- Same-die, same-package drop-in compatibility across the MAX 7000A family (vs EPM7128ATC100-7F)
- RoHS-compliant industrial variant available (vs EPM7128AETI100-10N)
Design Notes
The EPM7128ATI100-10 requires a clean 3.3V supply; place one 0.1 uF decoupling capacitor adjacent to every VCCINT/VCCIO pin pair and one bulk 10 uF tantalum or ceramic capacitor at the supply entry. The MAX 7000A draws up to 300 mA peak during ISP programming - ensure the regulator can sustain this transient. Power sequencing is not required, but supply rise time should be faster than 1 ms to guarantee correct power-on-reset of the EEPROM configuration logic.
Route JTAG signals (TCK, TMS, TDI, TDO, TRST) as a bus with no stubs, keeping the total trace length under 100 mm and using 22-33 ohm series termination at the driver when run length exceeds 50 mm. Maintain continuous ground return under the JTAG bus and avoid crossing any switching signals. Place the CPLD's VCCINT and VCCIO pins such that decoupling capacitors have minimal loop area; each capacitor should be no more than 3 mm from its associated supply pin.
Do not apply 5V to any output pin - the MAX 7000A I/O is 5V-tolerant only on input pins when VCCIO is 3.3V; outputs must never exceed VCCIO. Always enable the JTAG TRST pin (tie to logic-low through 1 kohm or drive low) to prevent inadvertent JTAG state-machine transitions at power-up. Verify that the BSDL file used for boundary-scan matches the exact -10 speed grade; mismatched speed grades produce false timing failures during manufacturing test.
The 10 ns tPD specification assumes a standard 50 pF load; for high-fanout designs (greater than 8 loads per output) use the slower tPD derating curves in the datasheet or buffer heavily-loaded nets. When interfacing to 5V receivers, confirm that VOH(min) at 3.3V exceeds the receiver VIH(min); some legacy TTL parts require 2.4V VOH which the MAX 7000A can meet only when I/O pins are configured as TTL-compatible (not CMOS) outputs.
Compliance Information
Legacy part; lead-free 'N' suffix variants (EPM7128AETI100-10N) are RoHS-compliant drop-in replacements. AEC-Q100 qualification not available for this family.
