EPM7128ELC84-20 vs EPM7128ELI84-20 Comparison
Detailed side-by-side comparison of EPM7128ELC84-20 by Altera and EPM7128ELI84-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
EPM7128ELI84-20 ⚠ Last Time BuySpecification Comparison
| Parameter | EPM7128ELC84-20 | EPM7128ELI84-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Series | MAX 7000 | — |
| Device Family | EPM7128 (CPLD) | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | 2500 | — |
| Number of User I/Os | 68 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Tolerance | 4.75 V to 5.25 V | — |
| Technology | CMOS, EEPROM-based (non-volatile) | EEPROM-based CMOS |
| Programmable Interface | IEEE Std. 1149.1 (JTAG) | — |
| Package Type | PLCC-84 (J-Lead, J-bend) | — |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount / Socketable (PLCC J-Lead) |
| Operating Temperature | 0C to +70C (commercial) | -40 °C to +85 °C (Industrial) |
| RoHS Status | Contains lead (pre-RoHS, SnPb finish) | Compliant (lead-free PLCC variant) |
| Family | — | MAX 7000 (Classic / MAX 7000B/E) |
| Device Name | — | EPM7128E |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum User I/Os | — | 68 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| Supply Voltage (VCCINT) | — | 5 V (4.75 V to 5.25 V for -20 speed grade) |
| Package | — | 84-pin PLCC (J-Lead) |
| Programming Interface | — | JTAG (IEEE 1149.1) + ISP |