EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
MPN: EPM7128ELI84-20 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.8 | $980.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.95 | $7,950.00 |
Drop-in alternatives for EPM7128ELI84-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128ELC84-20
β Drop-Inβ In Stock
$24.2 / Unit
View Datasheet βEPM7128ELI84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ELI84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC84-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC84-6N
β Drop-Inβ In Stock
$8.75 / Unit
View Datasheet βEPM7128ELI84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 (Classic / MAX 7000B/E) |
| Device Name | EPM7128E |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/Os | 68 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Maximum Operating Frequency (fCNT) | 62.5 MHz |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V for -20 speed grade) |
| Operating Temperature | -40 Β°C to +85 Β°C (Industrial) |
| Package | 84-pin PLCC (J-Lead) |
| Programming Interface | JTAG (IEEE 1149.1) + ISP |
| Technology | EEPROM-based CMOS |
| Mounting Type | Surface Mount / Socketable (PLCC J-Lead) |
| RoHS Status | Compliant (lead-free PLCC variant) |
EPM7128ELI84-20 Pin Configuration
| Pin 1 | I/O β User I/O (group 1) |
| Pin 2 | I/O β User I/O (group 1) |
| Pin 3 | I/O β User I/O (group 1) |
| Pin 4 | I/O β User I/O (group 1) |
| Pin 5 | I/O β User I/O (group 1) |
| Pin 6 | I/O β User I/O (group 1) |
| Pin 7 | I/O β User I/O (group 1) |
| Pin 8 | I/O β User I/O (group 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O (group 1) |
| Pin 11 | I/O β User I/O (group 1) |
| Pin 12 | I/O β User I/O (group 1) |
| Pin 13 | I/O β User I/O (group 1) |
| Pin 14 | I/O β User I/O (group 1) |
| Pin 15 | TDI β JTAG Test Data In |
| Pin 16 | TMS β JTAG Test Mode Select |
| Pin 17 | TCK β JTAG Test Clock |
| Pin 18 | I/O β User I/O (group 2) |
| Pin 19 | I/O β User I/O (group 2) |
| Pin 20 | I/O β User I/O (group 2) |
| Pin 21 | I/O β User I/O (group 2) |
| Pin 22 | VCCINT β Core supply voltage (+5V) |
| Pin 23 | I/O β User I/O (group 2) |
| Pin 24 | I/O β User I/O (group 2) |
| Pin 25 | I/O β User I/O (group 2) |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O (group 2) |
| Pin 28 | I/O β User I/O (group 2) |
| Pin 29 | I/O β User I/O (group 2) |
| Pin 30 | I/O β User I/O (group 2) |
| Pin 31 | GCLK β Global clock input |
| Pin 32 | I/O β User I/O (group 3) |
| Pin 33 | I/O β User I/O (group 3) |
| Pin 34 | I/O β User I/O (group 3) |
| Pin 35 | VCCIO β I/O supply voltage |
| Pin 36 | I/O β User I/O (group 3) |
| Pin 37 | I/O β User I/O (group 3) |
| Pin 38 | I/O β User I/O (group 3) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O (group 3) |
| Pin 41 | I/O β User I/O (group 3) |
| Pin 42 | OE1 β Output enable 1 (active low) |
| Pin 43 | GCLR β Global clear (active low) |
| Pin 44 | I/O β User I/O (group 4) |
| Pin 45 | I/O β User I/O (group 4) |
| Pin 46 | I/O β User I/O (group 4) |
| Pin 47 | I/O β User I/O (group 4) |
| Pin 48 | I/O β User I/O (group 4) |
| Pin 49 | I/O β User I/O (group 4) |
| Pin 50 | I/O β User I/O (group 4) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O (group 4) |
| Pin 53 | I/O β User I/O (group 4) |
| Pin 54 | I/O β User I/O (group 5) |
| Pin 55 | I/O β User I/O (group 5) |
| Pin 56 | I/O β User I/O (group 5) |
| Pin 57 | I/O β User I/O (group 5) |
| Pin 58 | I/O β User I/O (group 5) |
| Pin 59 | I/O β User I/O (group 5) |
| Pin 60 | I/O β User I/O (group 5) |
| Pin 61 | I/O β User I/O (group 5) |
| Pin 62 | I/O β User I/O (group 5) |
| Pin 63 | OE2 β Output enable 2 (active low) |
| Pin 64 | I/O β User I/O (group 6) |
| Pin 65 | I/O β User I/O (group 6) |
| Pin 66 | I/O β User I/O (group 6) |
| Pin 67 | VCCINT β Core supply voltage (+5V) |
| Pin 68 | I/O β User I/O (group 6) |
| Pin 69 | I/O β User I/O (group 6) |
| Pin 70 | I/O β User I/O (group 6) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O (group 6) |
| Pin 73 | I/O β User I/O (group 6) |
| Pin 74 | I/O β User I/O (group 6) |
| Pin 75 | I/O β User I/O (group 7) |
| Pin 76 | I/O β User I/O (group 7) |
| Pin 77 | I/O β User I/O (group 7) |
| Pin 78 | I/O β User I/O (group 7) |
| Pin 79 | I/O β User I/O (group 7) |
| Pin 80 | I/O β User I/O (group 7) |
| Pin 81 | I/O β User I/O (group 7) |
| Pin 82 | TDO β JTAG Test Data Out |
| Pin 83 | I/O β User I/O (group 8) |
| Pin 84 | I/O β User I/O (group 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ELI84-20 is suitable for 6 applications: Legacy 5V Microcontroller Bus Bridge, Address Decoding and Chip-Select Logic, Industrial Control State Machine, Telecom Backplane Glue Logic, Power Sequencing Controller, Peripheral Multiplexing and Protocol Conversion.
Legacy 5V Microcontroller Bus Bridge
The EPM7128ELI84-20's 68 user I/Os and 20ns tPD make it ideal for bridging 8/16-bit microcontroller buses to peripheral devices such as SRAM, FIFOs, and legacy ASICs. Its 5V VCCINT tolerance matches 5V MCU ports directly without level shifters, reducing BOM cost and board area. The 128 macrocells easily decode 24-bit address spaces and implement wait-state generators; each I/O has programmable slew-rate control that suppresses ringing on long PCB traces between the MCU and bus peripherals. Industrial temperature grade supports outdoor and factory-floor deployments.
Recommended
Address Decoding and Chip-Select Logic
The EPM7128ELI84-20 provides 2,500 usable gates which are well-suited for address decoding across complex memory maps β for example, generating up to 16 chip-select signals for a 1MB memory space partitioned into 64KB blocks. The 20ns propagation delay keeps the decoded CS valid within one 25MHz 8086/68000 bus cycle. Combined with the global OE and GCLR pins, multiple CPLDs can be cascaded to expand I/O count while preserving deterministic timing. The non-volatile EEPROM bitstream ensures the decoder map is correct at power-up with no configuration delay.
Recommended
Industrial Control State Machine
The EPM7128ELI84-20 is widely used in PLC and motor-control state machines where deterministic timing and industrial temperature range (-40Β°C to +85Β°C) are required. Its 8 LABs support parallel state machines for sequential process control, and the 62.5 MHz fCNT handles encoder inputs up to 62.5 MHz for high-resolution servo feedback. The JTAG ISP capability enables firmware updates in the field via the JTAG header, while the EEPROM retention guarantees bitstream integrity across power cycles and ESD events typical of factory-floor environments.
Recommended
Telecom Backplane Glue Logic
The EPM7128ELI84-20's 68 I/Os and 5V tolerance make it a workhorse in legacy telecom backplane cards where bus arbitration, framing, and interrupt-aggregation logic are required. The 84-PLCC socket allows hot-swap card replacement in fielded systems, and the JTAG ISP supports remote programming through test access ports on the backplane. Combined with external ECL/PECL interface buffers, the CPLD implements T1/E1 framer glue and clock-distribution fan-out. Industrial temp range meets NEBS environmental requirements for central-office deployments.
Recommended
Power Sequencing Controller
The EPM7128ELI84-20 is excellent for multi-rail power-sequencing controllers in line cards and modular systems. Its 128 macrocells track enable signals from PG (power-good) comparators and generate precisely delayed ENABLE pulses for downstream DC-DC converters, satisfying FPGA and ASIC rail-on sequencing rules. The programmable slew-rate control softens gate-drive edges for MOSFETs and minimizes EMI on high-current switching nodes. Industrial temp and 5V tolerance integrate cleanly with supervisory ICs and ORing controllers from Maxim, TI, and Linear Technology.
Recommended
Peripheral Multiplexing and Protocol Conversion
The EPM7128ELI84-20 implements protocol bridges between legacy interfaces such as UART, SPI, IΒ²C, and parallel buses. The 8 LABs handle parallel state machines for byte-level framing and CRC, while 68 I/Os support multiplexed data/address buses for FPGA coprocessors. The deterministic 20ns delay simplifies mixed-signal PCB routing where bus contention must be resolved in a single clock. JTAG ISP enables in-field firmware updates to support new peripheral variants without board rework.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ELI84-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128ELC84-20 | EPM7128ELI84-15 | EPM7128ELI84-10 | EPM7128SLC84-15N | EPM7128SLC84-6N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 15 ns | 10 ns | 15 ns | 6 ns |
| Max User I/Os | 68 | 68 | 68 | 68 | 68 | 68 |
| Core Voltage (VCCINT) | 5 V | 5 V | 5 V | 5 V | 3.3 V | 3.3 V |
| Operating Temperature | -40 Β°C to +85 Β°C (Industrial) | 0 Β°C to +70 Β°C (Commercial) | -40 Β°C to +85 Β°C (Industrial) | -40 Β°C to +85 Β°C (Industrial) | [DATA_NEEDED] | [DATA_NEEDED] |
| Family | MAX 7000B/E | MAX 7000B/E | MAX 7000B/E | MAX 7000B/E | MAX 7000S | MAX 7000S |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP |
| Approx. Unit Price (qty-1) | $12.50 | $11.00 | $14.20 | $15.80 | $13.40 | $16.00 |
Key Differentiators
- Industrial temperature range with 5V VCCINT tolerance (vs EPM7128ELC84-20)
- 20 ns tPD is faster than legacy 25/30 ns MAX 7000 parts (vs EPM7128SLC84-6N)
- MAX 7000B/E EEPROM bitstream is non-volatile and field-upgradable (vs MAX II SRAM-based CPLDs)
Design Notes
Estimated: The EPM7128ELI84-20 typically draws 50-200 mA from VCCINT (5V) depending on switching activity and configured logic utilization. At 100% utilization with 62.5 MHz toggle on all 68 I/Os, total ICC may approach 250 mA. Provide at least 0.1 Β΅F decoupling per VCCINT/VCCIO pin pair plus 10 Β΅F bulk at the socket. Place 0.1 Β΅F capacitors within 3 mm of each supply pin to suppress switching-current transients; the PLCC socket lead inductance is sufficient to cause ringing without local bypassing.
For 84-pin PLCC socketed designs, use a JEDEC-standard PLCC-84 SMT socket (e.g., 3M 8420-21B1 or equivalent) to enable field replacement and ISP upgrades. Maintain 50-ohm controlled impedance on output traces that toggle above 25 MHz, and add series 33Ξ© damping resistors at outputs driving long backplane traces to dampen reflections. The PLCC J-lead package has roughly 1 nH lead inductance β adequate for the 20 ns tPD timing margin but watch for ground-bounce on simultaneous-switching outputs.
When migrating an EPM7128ELI84-20 design to the EPM7128SLC84-xN family, remember that VCCINT drops from 5V to 3.3V β applying 5V to a 7000S part will permanently damage it. VCCIO remains 5V-tolerant on 7000S, but confirm voltage compatibility for each downstream device. Also note the global clear (GCLR) is active LOW on MAX 7000 family β invert the reset polarity in your RTL if migrating from a polarity-reversed design. Always program the security bit to lock the bitstream once the design is finalized, preventing readback of proprietary logic.
The MAX 7000 family uses TTL-compatible I/O thresholds; VIL β€ 0.8V and VIH β₯ 2.0V. For 5V tolerance when driving 3.3V peripherals from the EPM7128ELI84-20, add external 74HCT-series buffers rather than relying on the open-drain output option. The JTAG TCK should be pulled low through a 10 kΞ© resistor when the JTAG header is unpopulated to prevent floating-clock noise from corrupting in-system programming. For high-fanout signals, distribute them across LAB boundaries to avoid localized congestion on the PIA interconnect.
Compliance Information
RoHS-compliant lead-free 84-PLCC variant. AEC-Q100 not applicable for non-automotive CPLD. Conflict minerals status per Intel product declarations.
