EPM7128ELC84-20 - MAX 7000 CPLD, 128MC, 20ns, 5V, PLCC-84 | Altera
MPN: EPM7128ELC84-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.7 | $42.70 |
| 10 | $38.5 | $385.00 |
| 100 | $32.1 | $3,210.00 |
| 500 | $27.85 | $13,925.00 |
| 1,000 | $24.2 | $24,200.00 |
Drop-in alternatives for EPM7128ELC84-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128ELC84-15
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128ELC84-12
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EPM7128ELC84-10
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPM7128AELC84-10N
✅ Drop-In✓ In Stock
$10.45 / Unit
View Datasheet →EPM7128ELI84-20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPM7128SLC84-6N
✅ Drop-In✓ In Stock
$8.75 / Unit
View Datasheet →EPM7128ELC84-20 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000 |
| Device Family | EPM7128 (CPLD) |
| Number of Macrocells | 128 |
| Number of Usable Gates | 2500 |
| Number of User I/Os | 68 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Frequency (fCNT) | 62.5 MHz |
| Supply Voltage (VCC) | 5 V |
| Supply Voltage Tolerance | 4.75 V to 5.25 V |
| Technology | CMOS, EEPROM-based (non-volatile) |
| Programmable Interface | IEEE Std. 1149.1 (JTAG) |
| Package Type | PLCC-84 (J-Lead, J-bend) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Contains lead (pre-RoHS, SnPb finish) |
EPM7128ELC84-20 Pin Configuration
| Pin 1 | I/O — User I/O (macrocell pin) |
| Pin 2 | I/O — User I/O (macrocell pin) |
| Pin 3 | I/O — User I/O (macrocell pin) |
| Pin 4 | I/O — User I/O (macrocell pin) |
| Pin 5 | I/O — User I/O (macrocell pin) |
| Pin 6 | I/O — User I/O (macrocell pin) |
| Pin 7 | I/O — User I/O (macrocell pin) |
| Pin 8 | I/O — User I/O (macrocell pin) |
| Pin 9 | I/O — User I/O (macrocell pin) |
| Pin 10 | I/O — User I/O (macrocell pin) |
| Pin 11 | I/O — User I/O (macrocell pin) |
| Pin 12 | TDI — JTAG Test Data In |
| Pin 13 | I/O — User I/O (macrocell pin) |
| Pin 14 | I/O — User I/O (macrocell pin) |
| Pin 15 | VCC — 5V supply |
| Pin 16 | I/O — User I/O (macrocell pin) |
| Pin 17 | I/O — User I/O (macrocell pin) |
| Pin 18 | I/O — User I/O (macrocell pin) |
| Pin 19 | I/O — User I/O (macrocell pin) |
| Pin 20 | I/O — User I/O (macrocell pin) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O (macrocell pin) |
| Pin 23 | I/O — User I/O (macrocell pin) |
| Pin 24 | I/O — User I/O (macrocell pin) |
| Pin 25 | I/O — User I/O (macrocell pin) |
| Pin 26 | I/O — User I/O (macrocell pin) |
| Pin 27 | I/O — User I/O (macrocell pin) |
| Pin 28 | I/O — User I/O (macrocell pin) |
| Pin 29 | I/O — User I/O (macrocell pin) |
| Pin 30 | I/O — User I/O (macrocell pin) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O (macrocell pin) |
| Pin 33 | I/O — User I/O (macrocell pin) |
| Pin 34 | I/O — User I/O (macrocell pin) |
| Pin 35 | I/O — User I/O (macrocell pin) |
| Pin 36 | I/O — User I/O (macrocell pin) |
| Pin 37 | I/O — User I/O (macrocell pin) |
| Pin 38 | I/O — User I/O (macrocell pin) |
| Pin 39 | TMS — JTAG Test Mode Select |
| Pin 40 | VCC — 5V supply |
| Pin 41 | I/O — User I/O (macrocell pin) |
| Pin 42 | I/O — User I/O (macrocell pin) |
| Pin 43 | I/O — User I/O (macrocell pin) |
| Pin 44 | I/O — User I/O (macrocell pin) |
| Pin 45 | I/O — User I/O (macrocell pin) |
| Pin 46 | I/O — User I/O (macrocell pin) |
| Pin 47 | I/O — User I/O (macrocell pin) |
| Pin 48 | I/O — User I/O (macrocell pin) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O (macrocell pin) |
| Pin 51 | GCLK — Global Clock (dedicated input) |
| Pin 52 | OE2/GCLK2 — Global OE / Global Clock 2 (dedicated input) |
| Pin 53 | I/O — User I/O (macrocell pin) |
| Pin 54 | I/O — User I/O (macrocell pin) |
| Pin 55 | I/O — User I/O (macrocell pin) |
| Pin 56 | I/O — User I/O (macrocell pin) |
| Pin 57 | I/O — User I/O (macrocell pin) |
| Pin 58 | I/O — User I/O (macrocell pin) |
| Pin 59 | I/O — User I/O (macrocell pin) |
| Pin 60 | I/O — User I/O (macrocell pin) |
| Pin 61 | TCK — JTAG Test Clock (dedicated input) |
| Pin 62 | VCC — 5V supply |
| Pin 63 | I/O — User I/O (macrocell pin) |
| Pin 64 | I/O — User I/O (macrocell pin) |
| Pin 65 | I/O — User I/O (macrocell pin) |
| Pin 66 | I/O — User I/O (macrocell pin) |
| Pin 67 | I/O — User I/O (macrocell pin) |
| Pin 68 | I/O — User I/O (macrocell pin) |
| Pin 69 | I/O — User I/O (macrocell pin) |
| Pin 70 | I/O — User I/O (macrocell pin) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O (macrocell pin) |
| Pin 73 | I/O — User I/O (macrocell pin) |
| Pin 74 | OE1 — Global Output Enable 1 (dedicated input) |
| Pin 75 | I/O — User I/O (macrocell pin) |
| Pin 76 | I/O — User I/O (macrocell pin) |
| Pin 77 | I/O — User I/O (macrocell pin) |
| Pin 78 | I/O — User I/O (macrocell pin) |
| Pin 79 | I/O — User I/O (macrocell pin) |
| Pin 80 | I/O — User I/O (macrocell pin) |
| Pin 81 | TDO — JTAG Test Data Out |
| Pin 82 | VCC — 5V supply |
| Pin 83 | I/O — User I/O (macrocell pin) |
| Pin 84 | CLR — Global Clear (dedicated input) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ELC84-20 is suitable for 6 applications: Microprocessor Address Decoding & Glue Logic, Legacy Industrial Control & Automation, PC/104, ISA, and VME Bus Interface Cards, Telecom & Networking Backplane Glue, Prototyping & Educational Logic Development, Aerospace & Defense Avionics Interfaces.
Microprocessor Address Decoding & Glue Logic
The EPM7128ELC84-20 excels at address decoding and bus-interface glue logic in 5V microprocessor systems. Its 128 macro cells and 68 user I/Os are well-matched to combine multiple 74LS/74F-series decoders, latches, and arbiters into a single instant-on non-volatile device. With 20 ns tPD the part sits comfortably below the propagation budget of 8051, 80188, and 68k-era CPU buses running at 25 MHz. The 5V VCC and TTL-compatible I/O thresholds interface directly with 5V peripherals without level shifting, and the JTAG-supported in-system programmability allows late-stage PCB revisions without socket rework. Compared to discrete SSI/MSI logic, the CPLD reduces board area, lowers power via internal optimization, and provides documented timing that simplifies static-timing analysis.
Recommended
Legacy Industrial Control & Automation
In legacy industrial control racks, the EPM7128ELC84-20 consolidates PLC-style state machines, encoder quadrature decoders, and PWM generators into a single 5V programmable device. Its instant-on EEPROM configuration means no boot PROM and no watchdog reset is needed after power cycling, which is critical for unattended factory floor installations. The PLCC-84 J-Lead package accepts standard industrial sockets, simplifying field replacement without desoldering. With 2500 usable gates the CPLD handles multi-axis motion control logic, I/O debouncing, and serial protocol framing (RS-232/485 glue) in one chip. Industrial designers should choose the EPM7128ELI84-20 industrial-temperature variant for -40C to +85C environments; it is pin-compatible and drop-in replaceable on the same PLCC-84 footprint.
Recommended
PC/104, ISA, and VME Bus Interface Cards
PC/104, ISA, and VME expansion cards traditionally use CPLDs to implement bus arbitration, address mapping, and interrupt steering, and the EPM7128ELC84-20 was a popular choice for these applications. Its 5V TTL-compatible I/Os match the original ISA bus levels directly, and the 68 available user I/Os are sufficient for 16-bit data plus 24-bit address plus control-signal decoding in one device. The 20 ns tPD adds only 1 wait-state to 8 MHz ISA cycles and is adequate for 12 MHz designs. In-system JTAG programming allows the same card to be re-used across multiple SKUs by re-flashing the CPLD bitstream, reducing inventory cost. Designers migrating to PCI or PCIe must replace both connector and logic; the EPM7128 family is not suited to 3.3V/33 MHz PCI signaling.
Recommended
Telecom & Networking Backplane Glue
The EPM7128ELC84-20 was widely used in telecom line cards and networking backplanes for protocol conversion, clock-domain crossing, and TDM bus multiplexing. Its 5V tolerant I/Os interface with E1/T1 line-interface units (LIUs) and legacy TTL backplane logic, while the 8 LABs allow independent clock-domain FIFOs and rate-adaptation state machines. The deterministic 20 ns tPD simplifies meeting the hold-time requirements of source-synchronous backplane buses such as H.110 (CT Bus). Designers building new designs should note that the MAX 7000 family lacks 3.3V I/O, so ATCA or AMC backplanes will require the EPM7128SLC84-6N (3.3V core) or migration to MAX II/MAX V families with multi-voltage I/O support.
Recommended
Prototyping & Educational Logic Development
The EPM7128ELC84-20 is a staple of university digital-logic laboratories and hobbyist prototyping platforms because it provides enough macro cells (128) for full single-cycle RISC CPU cores, custom peripherals, and bus controllers while remaining instantly reprogrammable via inexpensive JTAG cables such as the Altera ByteBlaster. Its 5V supply eliminates level-shifting concerns when interfacing to legacy TTL lab equipment, and the PLCC-84 socket accepts standard 84-pin machine-tooled ZIF sockets for quick swap-out during lab sessions. The well-documented MAX 7000 family reference designs in the Altera University Program include UART cores, VGA controllers, and 7-segment display drivers that target this exact density. Educators should pair the EPM7128ELC84-20 with a stable 5V/1A linear regulator and 0.1 uF + 10 uF decoupling per VCC pin to ensure repeatable student results.
Recommended
Aerospace & Defense Avionics Interfaces
The EPM7128ELC84-20 has historically been used in avionics LRUs (Line Replaceable Units) for ARINC 429, MIL-STD-1553, and discrete-signal interface glue because its deterministic timing, instant-on EEPROM, and wide operating temperature (when paired with the I-grade variant) suit DO-254 and MIL-HDBK-454 design flows. The 68 user I/Os multiplex the receive/transmit channels of up to 4 ARINC 429 buses with parity generation, while the 8 LABs implement channel-decoding state machines. The PLCC-84 socket allows field replacement at forward operating bases without specialized rework tools. New avionics designs targeting DO-254 DAL A/B should consider the B-grade processed EPM7128ELI84-20 with extended temperature and traceability documentation, which is pin-compatible on the same PLCC-84 footprint.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ELC84-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128ELC84-15 | EPM7128ELC84-12 | EPM7128ELC84-10 | EPM7128AELC84-10N | EPM7128ELI84-20 | EPM7128SLC84-6N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) | PLCC-84 (J-Lead) |
| Supply Voltage (VCC) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| Propagation Delay (tPD) | 20 ns | 15 ns (-25%) | 12 ns (-40%) | 10 ns (-50%) | 10 ns (-50%) | 20 ns (0%) | 6 ns (-70%) |
| Maximum Frequency | 62.5 MHz | 83.3 MHz | 100 MHz | 125 MHz | 125 MHz | 62.5 MHz | 166.7 MHz |
| Number of Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Number of User I/Os | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C | 0C to +70C |
| RoHS Compliance | No (SnPb finish) | No (SnPb finish) | No (SnPb finish) | No (SnPb finish) | Yes (lead-free) | No (SnPb finish) | No (SnPb finish) |
Key Differentiators
- Slowest speed grade (-20) at lowest price point in MAX 7000 family (vs EPM7128ELC84-15)
- Drop-in industrial-temperature upgrade available (vs EPM7128ELI84-20)
- 5V core matches legacy TTL systems directly (vs EPM7128SLC84-6N)
Design Notes
The EPM7128ELC84-20 has multiple VCC pins (PLCC-84 pins 15, 40, 62, 82) that must each be decoupled with a 0.1 uF ceramic capacitor placed within 5 mm of the pin. Add a single bulk 10 uF tantalum or aluminum-polymer capacitor per VCC group to suppress switching transients during simultaneous-output switching (SSO). The I-grade variant draws similar quiescent current but extended temperature may increase I/O leakage; budget 50 mA typical ICC at full toggle.
The PLCC-84 J-Lead package (JEDEC MS-018) requires a 1.27 mm pitch land pattern with chamfered pin-1 indicator. For prototype work, install a through-hole PLCC socket (e.g., 3M 84-pin machined-pin socket) so the device can be swapped without desoldering - critical when working with obsolete parts where replacement stock may be limited. Production boards may solder the PLCC directly, but plan for a 1.5 mm keepout under the package body for cleaning and inspection.
Three pitfalls are commonly missed in MAX 7000 designs: (1) Unused I/O pins must be tied to GND through 10 kohm (or driven as outputs) to avoid floating-input quiescent-current spikes - leaving them open can add several mA of Icc. (2) The JTAG chain TDI->TDO order must match the BSDL file; reversing TDI/TDO causes programming failure but the device still functions normally. (3) The MAX 7000 family is 5V-only on the E-suffix parts - mixing 3.3V peripherals on the I/O bank requires the EPM7128SLC variant instead; do not exceed 5.25 V on VCC.
Compliance Information
EPM7128ELC84-20 is a pre-RoHS part with SnPb finish on PLCC-84 leads; REACH compliance unknown per Intel/Altera product page. For RoHS-compliant equivalents choose EPM7128AELC84-10N in the same PLCC-84 footprint.
